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-rw-r--r--src/arch/i386/include/arch/asm.h15
-rw-r--r--src/arch/i386/include/arch/intel.h313
-rw-r--r--src/arch/i386/lib/c_start.S12
-rw-r--r--src/cpu/i386/entry16.inc16
-rw-r--r--src/cpu/i386/entry32.inc8
-rw-r--r--src/cpu/i386/reset32.inc6
-rw-r--r--src/mainboard/amd/solo/auto.c10
7 files changed, 32 insertions, 348 deletions
diff --git a/src/arch/i386/include/arch/asm.h b/src/arch/i386/include/arch/asm.h
index 122b299d23..f41ec166e2 100644
--- a/src/arch/i386/include/arch/asm.h
+++ b/src/arch/i386/include/arch/asm.h
@@ -1,19 +1,6 @@
#ifndef ASM_H
#define ASM_H
-#define ASSEMBLER
-
-/*
- * Bootstrap code for the STPC Consumer
- * Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
- *
- */
-
-#define I386_ALIGN_TEXT 0
-#define I386_ALIGN_DATA 0
-
-#define STATIC(x) .align I386_ALIGN_TEXT; EXT(x):
-#define GLOBAL(x) .globl EXT(x); STATIC(x)
-#define ENTRY(x) .text; GLOBAL(x)
+#define ASSEMBLER 1
#endif /* ASM_H */
diff --git a/src/arch/i386/include/arch/intel.h b/src/arch/i386/include/arch/intel.h
index e46e881558..d276b32596 100644
--- a/src/arch/i386/include/arch/intel.h
+++ b/src/arch/i386/include/arch/intel.h
@@ -29,19 +29,6 @@ it with the version available from LANL.
*
*/
-/*
- * Config registers.
- */
-/* yeah, yeah, I know these are macros, which is bad. Don't forget:
- * we have almost no assembly, so I am not worrying just yet about this.
- * we'll fix it someday if we care. My guess is we won't.
- */
-
-/* well we want functions. But first we want to see it work at all. */
-#undef FUNCTIONS
-#ifndef FUNCTIONS
-
-
#define RET_LABEL(label) \
jmp label##_done
@@ -58,310 +45,10 @@ label##_done:
jmp *%esp
-#define DELAY(x) mov x, %ecx ;\
- 1: loop 1b ;\
-
-
- /*
- * Macro: PCI_WRITE_CONFIG_BYTE
- * Arguments: %eax address to write to (includes bus, device, function, &offset)
- * %dl byte to write
- *
- * Results: none
- *
- * Trashed: %eax, %edx
- * Effects: writes a single byte to pci config space
- *
- * Notes: This routine is optimized for minimal register usage.
- * And the tricks it does cannot scale beyond writing a single byte.
- *
- * What it does is almost simple.
- * It preserves %eax (baring special bits) until it is written
- * out to the appropriate port. And hides the data byte
- * in the high half of edx.
- *
- * In %edx[3] it stores the byte to write.
- * In %edx[2] it stores the lower three bits of the address.
- */
-
-
-#define PCI_WRITE_CONFIG_BYTE \
- shll $8, %edx ; \
- movb %al, %dl ; \
- andb $0x3, %dl ; \
- shll $16, %edx ; \
- \
- orl $0x80000000, %eax ; \
- andl $0xfffffffc, %eax ; \
- movw $0xcf8, %dx ; \
- outl %eax, %dx ; \
- \
- shrl $16, %edx ; \
- movb %dh, %al ; \
- movb $0, %dh ; \
- addl $0xcfc, %edx ; \
- outb %al, %dx
-
-
- /*
- * Macro: PCI_WRITE_CONFIG_WORD
- * Arguments: %eax address to write to (includes bus, device, function, &offset)
- * %ecx word to write
- *
- * Results: none
- *
- * Trashed: %eax, %edx
- * Preserved: %ecx
- * Effects: writes a single byte to pci config space
- *
- * Notes: This routine is optimized for minimal register usage.
- *
- * What it does is almost simple.
- * It preserves %eax (baring special bits) until it is written
- * out to the appropriate port. And hides the least significant
- * bits of the address in the high half of edx.
- *
- * In %edx[2] it stores the lower three bits of the address.
- */
-
-
-#define PCI_WRITE_CONFIG_WORD \
- movb %al, %dl ; \
- andl $0x3, %edx ; \
- shll $16, %edx ; \
- \
- orl $0x80000000, %eax ; \
- andl $0xfffffffc, %eax ; \
- movw $0xcf8, %dx ; \
- outl %eax, %dx ; \
- \
- shrl $16, %edx ; \
- movl %ecx, %eax ; \
- addl $0xcfc, %edx ; \
- outw %ax, %dx
-
-
-
- /*
- * Macro: PCI_WRITE_CONFIG_DWORD
- * Arguments: %eax address to write to (includes bus, device, function, &offset)
- * %ecx dword to write
- *
- * Results: none
- *
- * Trashed: %eax, %edx
- * Preserved: %ecx
- * Effects: writes a single byte to pci config space
- *
- * Notes: This routine is optimized for minimal register usage.
- *
- * What it does is almost simple.
- * It preserves %eax (baring special bits) until it is written
- * out to the appropriate port. And hides the least significant
- * bits of the address in the high half of edx.
- *
- * In %edx[2] it stores the lower three bits of the address.
- */
-
-
-#define PCI_WRITE_CONFIG_DWORD \
- movb %al, %dl ; \
- andl $0x3, %edx ; \
- shll $16, %edx ; \
- \
- orl $0x80000000, %eax ; \
- andl $0xfffffffc, %eax ; \
- movw $0xcf8, %dx ; \
- outl %eax, %dx ; \
- \
- shrl $16, %edx ; \
- movl %ecx, %eax ; \
- addl $0xcfc, %edx ; \
- outl %eax, %dx
-
-
-
-
- /*
- * Macro: PCI_READ_CONFIG_BYTE
- * Arguments: %eax address to read from (includes bus, device, function, &offset)
- *
- * Results: %al Byte read
- *
- * Trashed: %eax, %edx
- * Effects: reads a single byte from pci config space
- *
- * Notes: This routine is optimized for minimal register usage.
- *
- * What it does is almost simple.
- * It preserves %eax (baring special bits) until it is written
- * out to the appropriate port. And hides the least significant
- * bits of the address in the high half of edx.
- *
- * In %edx[2] it stores the lower three bits of the address.
- */
-
-
-#define PCI_READ_CONFIG_BYTE \
- movb %al, %dl ; \
- andl $0x3, %edx ; \
- shll $16, %edx ; \
- \
- orl $0x80000000, %eax ; \
- andl $0xfffffffc, %eax ; \
- movw $0xcf8, %dx ; \
- outl %eax, %dx ; \
- \
- shrl $16, %edx ; \
- addl $0xcfc, %edx ; \
- inb %dx, %al
-
-
-
- /*
- * Macro: PCI_READ_CONFIG_WORD
- * Arguments: %eax address to read from (includes bus, device, function, &offset)
- *
- * Results: %ax word read
- *
- * Trashed: %eax, %edx
- * Effects: reads a 2 bytes from pci config space
- *
- * Notes: This routine is optimized for minimal register usage.
- *
- * What it does is almost simple.
- * It preserves %eax (baring special bits) until it is written
- * out to the appropriate port. And hides the least significant
- * bits of the address in the high half of edx.
- *
- * In %edx[2] it stores the lower three bits of the address.
- */
-
-
-#define PCI_READ_CONFIG_WORD \
- movb %al, %dl ; \
- andl $0x3, %edx ; \
- shll $16, %edx ; \
- \
- orl $0x80000000, %eax ; \
- andl $0xfffffffc, %eax ; \
- movw $0xcf8, %dx ; \
- outl %eax, %dx ; \
- \
- shrl $16, %edx ; \
- addl $0xcfc, %edx ; \
- inw %dx, %ax
-
-
-
- /*
- * Macro: PCI_READ_CONFIG_DWORD
- * Arguments: %eax address to read from (includes bus, device, function, &offset)
- *
- * Results: %eax
- *
- * Trashed: %edx
- * Effects: reads 4 bytes from pci config space
- *
- * Notes: This routine is optimized for minimal register usage.
- *
- * What it does is almost simple.
- * It preserves %eax (baring special bits) until it is written
- * out to the appropriate port. And hides the least significant
- * bits of the address in the high half of edx.
- *
- * In %edx[2] it stores the lower three bits of the address.
- */
-
-
-#define PCI_READ_CONFIG_DWORD \
- movb %al, %dl ; \
- andl $0x3, %edx ; \
- shll $16, %edx ; \
- \
- orl $0x80000000, %eax ; \
- andl $0xfffffffc, %eax ; \
- movw $0xcf8, %dx ; \
- outl %eax, %dx ; \
- \
- shrl $16, %edx ; \
- addl $0xcfc, %edx ; \
- inl %dx, %eax
-
-
-
-
-#define CS_READ(which) \
- mov $0x80000000,%eax ; \
- mov which,%ax ; \
- and $0xfc,%al /* clear bits 1-0 */ ; \
- mov $0xcf8,%dx /* port 0xcf8 ?*/ ; \
- outl %eax,%dx /* open up CS config */ ; \
- add $0x4,%dl /* 0xcfc data port 0 */ ; \
- mov which,%al ; \
- and $0x3,%al /* only bits 1-0 */ ; \
- add %al,%dl ; \
- inb %dx,%al /* read */ ; \
-
-
-#define CS_WRITE(which, data) \
- mov $0x80000000,%eax /* 32bit word with bit 31 set */ ; \
- mov which,%ax /* put the reg# in the low part */ ; \
- and $0xfc,%al /* dword align the reg# */ ; \
- mov $0xcf8,%dx /* enable port */ ; \
- outl %eax,%dx ; \
- add $0x4,%dl /* 1st data port */ ; \
- mov which,%ax /* register# */ ; \
- and $0x3,%ax ; \
- add %al,%dl ; \
- mov data, %al ; \
- outb %al,%dx /* write to reg */
-
-#define REGBIS(which, bis) \
- CS_READ(which) ;\
- movb bis, %cl ;\
- orb %al, %cl ;\
- CS_WRITE(which, %cl)
-
-#define REGBIC(which, bic) \
- CS_READ(which) ;\
- movb bic, %cl ;\
- notb %cl ;\
- andb %al, %cl ;\
- CS_WRITE(which, %cl)
-
-
-/* macro to BIC and BIS a reg. calls read a reg,
- * does a BIC and then a BIS on it.
- * to clear no bits, make BIC 0.
- * to set no bits, make BIS 0
- */
-#define REGBICBIS(which, bic, bis) \
- CS_READ(which) ;\
- movb bic, %cl ;\
- notb %cl ;\
- andb %cl, %al ;\
- movb bis, %cl ;\
- orb %al, %cl ;\
- CS_WRITE(which, %cl)
-
-#else
-NO FUNCTIONS YET!
-#endif
-
-
-
/* originally this macro was from STPC BIOS */
#define intel_chip_post_macro(value) \
movb $value, %al ; \
outb %al, $0x80
-#define INTEL_PDATA_MAGIC 0xdeadbeef
-
-/* SLOW_DOWN_IO is a delay we can use that is roughly cpu neutral,
- * and can be used before memory or timer chips come up.
- * Since this hits the isa bus it's roughly
- */
-#define SLOW_DOWN_IO inb $0x80, %al
#endif /* ROM_INTEL_H */
diff --git a/src/arch/i386/lib/c_start.S b/src/arch/i386/lib/c_start.S
index f5ca3388f8..48c1514a1e 100644
--- a/src/arch/i386/lib/c_start.S
+++ b/src/arch/i386/lib/c_start.S
@@ -20,16 +20,16 @@ _start:
intel_chip_post_macro(0x13) /* post 12 */
/** clear stack */
- leal EXT(_stack), %edi
- movl $EXT(_estack), %ecx
+ leal _stack, %edi
+ movl $_estack, %ecx
subl %edi, %ecx
xorl %eax, %eax
rep
stosb
/** clear bss */
- leal EXT(_bss), %edi
- movl $EXT(_ebss), %ecx
+ leal _bss, %edi
+ movl $_ebss, %ecx
subl %edi, %ecx
jz .Lnobss
xorl %eax, %eax
@@ -50,7 +50,7 @@ _start:
1: addl $4, %ebx
cmpl $(MAX_CPUS << 2), %ebx
je 2
- cmpl %eax, EXT(initial_apicid)(%ebx)
+ cmpl %eax, initial_apicid(%ebx)
jne 1b
2: shrl $2, %ebx
@@ -78,7 +78,7 @@ _start:
movl %ebp, %esp
/* The boot_complete flag has already been pushed */
- call EXT(hardwaremain)
+ call hardwaremain
/*NOTREACHED*/
.Lhlt:
intel_chip_post_macro(0xee) /* post fe */
diff --git a/src/cpu/i386/entry16.inc b/src/cpu/i386/entry16.inc
index c357504735..7ab3ff3bf0 100644
--- a/src/cpu/i386/entry16.inc
+++ b/src/cpu/i386/entry16.inc
@@ -28,10 +28,10 @@ it with the version available from LANL.
/* .section ".rom.text" */
#include <arch/rom_segs.h>
.code16
-.globl EXT(_start)
-.type EXT(_start), @function
+.globl _start
+.type _start, @function
-EXT(_start):
+_start:
cli
/* thanks to kmliu@sis.tw.com for this TBL fix ... */
@@ -84,7 +84,7 @@ EXT(_start):
movw %cs, %ax
shlw $4, %ax
- movw $EXT(gdtptr16_offset), %bx
+ movw $gdtptr16_offset, %bx
subw %ax, %bx
data32 lgdt %cs:(%bx)
@@ -101,12 +101,12 @@ EXT(_start):
*/
.align 4
-.globl EXT(gdtptr16)
-EXT(gdtptr16):
+.globl gdtptr16
+gdtptr16:
.word gdt_end - gdt -1 /* compute the table limit */
.long gdt /* we know the offset */
-.globl EXT(_estart)
-EXT(_estart):
+.globl _estart
+_estart:
.code32
diff --git a/src/cpu/i386/entry32.inc b/src/cpu/i386/entry32.inc
index 8ccd638e95..6f55f00203 100644
--- a/src/cpu/i386/entry32.inc
+++ b/src/cpu/i386/entry32.inc
@@ -6,10 +6,10 @@
.code32
.align 4
-.globl EXT(gdtptr)
+.globl gdtptr
gdt:
-EXT(gdtptr):
+gdtptr:
.word gdt_end - gdt -1 /* compute the table limit */
.long gdt /* we know the offset */
.word 0
@@ -37,8 +37,8 @@ gdt_end:
* cache will be reloaded.
*/
.align 4
-.globl EXT(protected_start)
-EXT(protected_start):
+.globl protected_start
+protected_start:
lgdt %cs:gdtptr
ljmp $ROM_CODE_SEG, $__protected_start
diff --git a/src/cpu/i386/reset32.inc b/src/cpu/i386/reset32.inc
index ec743b70cc..42c68cc770 100644
--- a/src/cpu/i386/reset32.inc
+++ b/src/cpu/i386/reset32.inc
@@ -1,10 +1,10 @@
.section ".reset"
.code16
-.globl EXT(reset_vector)
-EXT(reset_vector):
+.globl reset_vector
+reset_vector:
. = 0x8;
.code32
- jmp EXT(protected_start)
+ jmp protected_start
.previous
diff --git a/src/mainboard/amd/solo/auto.c b/src/mainboard/amd/solo/auto.c
index 17eb03e7bc..befce49a8c 100644
--- a/src/mainboard/amd/solo/auto.c
+++ b/src/mainboard/amd/solo/auto.c
@@ -7,6 +7,16 @@
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+
+static void memreset_setup(const struct mem_controller *ctrl)
+{
+}
+
+static void memreset(const struct mem_controller *ctrl)
+{
+}
+
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 10:45:21 +0000