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diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 134166f2e0..c6d6c362a0 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -85,7 +85,6 @@ The boards in this section are not real mainboards, but emulators. ## Intel - [DG43GT](intel/dg43gt.md) -- [IceLake RVP](intel/icelake_rvp.md) - [KBLRVP11](intel/kblrvp11.md) ## Kontron diff --git a/Documentation/mainboard/intel/icelake_rvp.md b/Documentation/mainboard/intel/icelake_rvp.md deleted file mode 100644 index 514ba6b4dd..0000000000 --- a/Documentation/mainboard/intel/icelake_rvp.md +++ /dev/null @@ -1,40 +0,0 @@ -# Intel Ice Lake RVP (Reference Validation Platform) - -This page describes how to run coreboot on the Intel icelake_rvp board. - -Ice Lake RVP is based on Intel Ice Lake platform, please refer to below link to get more details -```eval_rst -:doc:`../../soc/intel/icelake/iceLake_coreboot_development` -``` - -## Building coreboot - -* Follow build instructions mentioned in Ice Lake document -```eval_rst -:doc:`../../soc/intel/icelake/iceLake_coreboot_development` -``` - -* The default options for this board should result in a fully working image: -```bash - # echo "CONFIG_VENDOR_INTEL=y" > .config - # echo "CONFIG_BOARD_INTEL_ICELAKE_RVPU=y" >> .config - # make olddefconfig && make -``` - -## Flashing coreboot - -```eval_rst -+---------------------+------------+ -| Type | Value | -+=====================+============+ -| Socketed flash | no | -+---------------------+------------+ -| Vendor | Winbond | -+---------------------+------------+ -| Size | 32 MiB | -+---------------------+------------+ -| Internal flashing | yes | -+---------------------+------------+ -| External flashing | yes | -+---------------------+------------+ -``` diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md index 8ac7e80f1f..5872202750 100644 --- a/Documentation/security/vboot/list_vboot.md +++ b/Documentation/security/vboot/list_vboot.md @@ -290,8 +290,6 @@ - Emerald Lake 2 CRB - Galileo - Glkrvp -- Icelake U DDR4/LPDDR4 RVP -- Icelake Y LPDDR4 RVP - Jasperlake DDR4/LPDDR4 RVP - Jasperlake DDR4/LPDDR4 RVP with Chrome EC - Kabylake LPDDR3 RVP3 diff --git a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md deleted file mode 100644 index 214733140b..0000000000 --- a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md +++ /dev/null @@ -1,67 +0,0 @@ -# Intel Ice Lake coreboot development - -## Introduction - -This document captures the coreboot development strategy for Intel SoC named Ice lake. - -The Ice Lake processor family is the next generation Intel® Core processor family. -These processors are built using Intel's 10 nm+ process. - -* [What is Ice Lake?](https://www.intel.in/content/www/in/en/design/products-and-solutions/processors-and-chipsets/ice-lake/overview.html) - -## Development Strategy - -Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel common code development model". - -1. Intel develops initial Firmware code for Ice Lake SoC. - -2. Additionally provides Firmware code support for Intel Reference Platform (RVP), known as Ice lake RVP with same SoC. - ```eval_rst - :doc:`../../../mainboard/intel/icelake_rvp` - ``` - -### Summary: -* SoC is Ice Lake. -* Reference platform is icelake_rvp. -* OEM board is Dragonegg. - -## Create coreboot Image - -1. Clone latest coreboot code as below - ```bash - $ git clone https://review.coreboot.org/coreboot.git - ``` - -2. Place blobs (ucode, me.bin and FSP packages) in appropriate locations - - Note: - Consider the fact that ucode and ME kit for Ice Lake SoC will be available from Intel VIP site. - After product launch, FSP binary will be available externally as any other program. - -3. Create coreboot .config - -4. Build toolchain - ```bash - CPUS=$(nproc--ignore=1) make crossgcc-i386 iasl - ``` - -5. Build image - ```bash - $ make # the image is generated as build/coreboot.rom - ``` - -## Flashing coreboot - -Flashing mechanism might be different between Intel RVP (Reference Validation Platform) and Chromebooks: - -* Make use of dediprog while flashing coreboot image on Intel-RVP -* For Chromebook related platform like dragonegg, one can flash via servo: - -```bash - $ dut-control spi2_vref:pp3300 spi2_buf_en:on spi2_buf_on_flex_en:on warm_reset:on - $ sudo flashrom -n -p ft2232_spi:type=servo-v2 -w <bios_image> - $ dut-control spi2_vref:off spi2_buf_en:off spi2_buf_on_flex_en:off warm_reset:off -``` -### References -* [flashrom](https://flashrom.org/Flashrom) -* [Servo](https://www.chromium.org/chromium-os/servo) diff --git a/Documentation/soc/intel/icelake/index.md b/Documentation/soc/intel/icelake/index.md deleted file mode 100644 index 71397d21bf..0000000000 --- a/Documentation/soc/intel/icelake/index.md +++ /dev/null @@ -1,7 +0,0 @@ -# Intel Ice Lake SOC-specific documentation - -This section contains documentation about coreboot on specific Intel "Ice Lake" SOCs. - -## Ice Lake coreboot development - -- [Ice Lake coreboot development](iceLake_coreboot_development.md) diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index 8da9cacc6e..b10b28885b 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -7,7 +7,6 @@ This section contains documentation about coreboot on specific Intel SOCs. - [Common code development strategy](code_development_model/code_development_model.md) - [FSP](fsp/index.md) - [Broadwell](broadwell/index.md) -- [Ice Lake/9th Gen Core-i series](icelake/index.md) - [MP Initialization](mp_init/mp_init.md) - [Microcode Updates](microcode.md) - [Firmware Interface Table](fit.md) diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 381f20c1ac..4e23c5bb30 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -36,8 +36,6 @@ #define CPUID_COFFEELAKE_B0 0x906eb #define CPUID_COFFEELAKE_P0 0x906ec #define CPUID_COFFEELAKE_R0 0x906ed -#define CPUID_ICELAKE_A0 0x706e0 -#define CPUID_ICELAKE_B0 0x706e1 #define CPUID_JASPERLAKE_A0 0x906c0 #define CPUID_COMETLAKE_U_A0 0xa0660 #define CPUID_COMETLAKE_U_K0_S0 0xa0661 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 5668053d1b..15a41ce072 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2908,13 +2908,6 @@ #define PCI_DID_INTEL_CNP_H_LPC_QM370 0xa30c #define PCI_DID_INTEL_CNP_H_LPC_HM370 0xa30d #define PCI_DID_INTEL_CNP_H_LPC_CM246 0xa30e -#define PCI_DID_INTEL_ICL_U_SUPER_U_ESPI 0x3480 -#define PCI_DID_INTEL_ICL_U_SUPER_U_ESPI_REV0 0x3481 -#define PCI_DID_INTEL_ICL_U_PREMIUM_ESPI 0x3482 -#define PCI_DID_INTEL_ICL_BASE_Y_ESPI 0x3483 -#define PCI_DID_INTEL_ICL_BASE_U_ESPI 0x3484 -#define PCI_DID_INTEL_ICL_Y_PREMIUM_ESPI 0x3487 -#define PCI_DID_INTEL_ICL_SUPER_Y_ESPI 0x3486 #define PCI_DID_INTEL_CMP_SUPER_U_LPC 0x0281 #define PCI_DID_INTEL_CMP_PREMIUM_Y_LPC 0x0283 #define PCI_DID_INTEL_CMP_PREMIUM_U_LPC 0x0284 @@ -3904,22 +3897,6 @@ #define PCI_DID_INTEL_CFL_S_GT2_3 0x3e9a #define PCI_DID_INTEL_CFL_S_GT2_4 0x3e91 #define PCI_DID_INTEL_CFL_S_GT2_5 0x3e96 -#define PCI_DID_INTEL_ICL_GT0_ULT 0x8A70 -#define PCI_DID_INTEL_ICL_GT0_5_ULT 0x8A71 -#define PCI_DID_INTEL_ICL_GT1_ULT 0x8A40 -#define PCI_DID_INTEL_ICL_GT2_ULX_0 0x8A50 -#define PCI_DID_INTEL_ICL_GT2_ULX_1 0x8A5D -#define PCI_DID_INTEL_ICL_GT2_ULT_1 0x8A5B -#define PCI_DID_INTEL_ICL_GT2_ULX_2 0x8A5C -#define PCI_DID_INTEL_ICL_GT2_ULT_2 0x8A5A -#define PCI_DID_INTEL_ICL_GT2_ULX_3 0x8A51 -#define PCI_DID_INTEL_ICL_GT2_ULT_3 0x8A52 -#define PCI_DID_INTEL_ICL_GT2_ULX_4 0x8A53 -#define PCI_DID_INTEL_ICL_GT2_ULT_4 0x8A54 -#define PCI_DID_INTEL_ICL_GT2_ULX_5 0x8A55 -#define PCI_DID_INTEL_ICL_GT2_ULT_5 0x8A56 -#define PCI_DID_INTEL_ICL_GT2_ULX_6 0x8A57 -#define PCI_DID_INTEL_ICL_GT3_ULT 0x8A62 #define PCI_DID_INTEL_CML_GT1_ULT_1 0x9B21 #define PCI_DID_INTEL_CML_GT1_ULT_2 0x9B2A #define PCI_DID_INTEL_CML_GT2_ULT_1 0x9B41 @@ -4050,10 +4027,6 @@ #define PCI_DID_INTEL_CFL_ID_S_S_4 0x3e33 #define PCI_DID_INTEL_CFL_ID_S_S_6 0x3eca #define PCI_DID_INTEL_CFL_ID_S_S_8 0x3e32 -#define PCI_DID_INTEL_ICL_ID_U 0x8A12 -#define PCI_DID_INTEL_ICL_ID_U_2_2 0x8A02 -#define PCI_DID_INTEL_ICL_ID_Y 0x8A10 -#define PCI_DID_INTEL_ICL_ID_Y_2 0x8A00 #define PCI_DID_INTEL_CML_ULT 0x9B61 #define PCI_DID_INTEL_CML_ULT_2_2 0x9B71 #define PCI_DID_INTEL_CML_ULT_6_2 0x9B51 @@ -4210,7 +4183,6 @@ #define PCI_DID_INTEL_KBL_P2SB 0xa2a0 #define PCI_DID_INTEL_CNL_P2SB 0x9da0 #define PCI_DID_INTEL_CNP_H_P2SB 0xa320 -#define PCI_DID_INTEL_ICL_P2SB 0x34a0 #define PCI_DID_INTEL_CMP_P2SB 0x02a0 #define PCI_DID_INTEL_CMP_H_P2SB 0x06a0 #define PCI_DID_INTEL_TGL_P2SB 0xa0a0 @@ -4230,7 +4202,6 @@ #define PCI_DID_INTEL_GLK_SRAM 0x31ec #define PCI_DID_INTEL_CNL_SRAM 0x9def #define PCI_DID_INTEL_CNP_H_SRAM 0xa36f -#define PCI_DID_INTEL_ICL_SRAM 0x34ef #define PCI_DID_INTEL_CMP_SRAM 0x02ef #define PCI_DID_INTEL_CMP_H_SRAM 0x06ef #define PCI_DID_INTEL_TGL_H_SRAM 0x43ef @@ -4252,7 +4223,6 @@ #define PCI_DID_INTEL_LWB_AUDIO_SUPER 0xa270 #define PCI_DID_INTEL_KBL_AUDIO 0x9d71 #define PCI_DID_INTEL_CNP_H_AUDIO 0xa348 -#define PCI_DID_INTEL_ICL_AUDIO 0x34c8 #define PCI_DID_INTEL_CMP_AUDIO 0x02c8 #define PCI_DID_INTEL_CMP_H_AUDIO 0x06c8 #define PCI_DID_INTEL_BSW_AUDIO 0x2284 @@ -4302,7 +4272,6 @@ #define PCI_DID_INTEL_LWB_CSE1_SUPER 0xa23b #define PCI_DID_INTEL_LWB_CSE2_SUPER 0xa23e #define PCI_DID_INTEL_CNP_H_CSE0 0xa360 -#define PCI_DID_INTEL_ICL_CSE0 0x34e0 #define PCI_DID_INTEL_CMP_CSE0 0x02e0 #define PCI_DID_INTEL_CMP_H_CSE0 0x06e0 #define PCI_DID_INTEL_TGL_CSE0 0xa0e0 @@ -4358,7 +4327,6 @@ #define PCI_DID_INTEL_SKL_SD 0x9d2d #define PCI_DID_INTEL_CNL_SD 0x9df5 #define PCI_DID_INTEL_CNP_H_SD 0xa375 -#define PCI_DID_INTEL_ICL_SD 0x34f8 #define PCI_DID_INTEL_CMP_SD 0x02f5 #define PCI_DID_INTEL_CMP_H_SD 0x06f5 #define PCI_DID_INTEL_MCC_SD 0x4b48 @@ -4456,7 +4424,6 @@ #define PCI_DID_INTEL_CNL_LP_CNVI_WIFI 0x9df0 #define PCI_DID_INTEL_CNL_H_CNVI_WIFI 0xa370 #define PCI_DID_INTEL_GLK_CNVI_WIFI 0x31dc -#define PCI_DID_INTEL_ICL_CNVI_WIFI 0x34f0 #define PCI_DID_INTEL_JSL_CNVI_WIFI_0 0x4df0 #define PCI_DID_INTEL_JSL_CNVI_WIFI_1 0x4df1 #define PCI_DID_INTEL_JSL_CNVI_WIFI_2 0x4df2 diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig deleted file mode 100644 index 24a15bed5d..0000000000 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ /dev/null @@ -1,52 +0,0 @@ -if BOARD_INTEL_ICELAKE_RVPU || BOARD_INTEL_ICELAKE_RVPY - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_16384 - select EC_ACPI - select HAVE_SPD_IN_CBFS - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select MAINBOARD_HAS_CHROMEOS - select HAVE_SPD_IN_CBFS - select DRIVERS_I2C_HID - select DRIVERS_I2C_GENERIC - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select SOC_INTEL_ICELAKE - select MAINBOARD_USES_IFD_EC_REGION - select INTEL_LPSS_UART_FOR_CONSOLE - -config MAINBOARD_DIR - default "intel/icelake_rvp" - -config VARIANT_DIR - default "icl_u" if BOARD_INTEL_ICELAKE_RVPU - default "icl_y" if BOARD_INTEL_ICELAKE_RVPY - -config MAINBOARD_PART_NUMBER - default "Icelake RVP" - -config MAINBOARD_FAMILY - string - default "Intel_icelake_rvp" - -config MAX_CPUS - int - default 8 - -config DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" - -config DIMM_SPD_SIZE - default 512 - -config VBOOT - select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA - -config UART_FOR_CONSOLE - int - default 2 -endif diff --git a/src/mainboard/intel/icelake_rvp/Kconfig.name b/src/mainboard/intel/icelake_rvp/Kconfig.name deleted file mode 100644 index 9ba17a65be..0000000000 --- a/src/mainboard/intel/icelake_rvp/Kconfig.name +++ /dev/null @@ -1,4 +0,0 @@ -config BOARD_INTEL_ICELAKE_RVPU - bool "Icelake U DDR4/LPDDR4 RVP" -config BOARD_INTEL_ICELAKE_RVPY - bool "Icelake Y LPDDR4 RVP" diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc deleted file mode 100644 index 60551c5213..0000000000 --- a/src/mainboard/intel/icelake_rvp/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -subdirs-y += spd - -bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c - -verstage-$(CONFIG_CHROMEOS) += chromeos.c - -romstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-y += romstage_fsp_params.c -romstage-y += board_id.c - -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c -ramstage-y += mainboard.c -ramstage-y += board_id.c - -subdirs-y += variants/baseboard -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include - -subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/icelake_rvp/board_id.c b/src/mainboard/intel/icelake_rvp/board_id.c deleted file mode 100644 index 0ab7e6a5e9..0000000000 --- a/src/mainboard/intel/icelake_rvp/board_id.c +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#include "board_id.h" -#include <boardid.h> -#include <ec/acpi/ec.h> -#include <stdint.h> -#include <ec/google/chromeec/ec.h> - -static int get_board_id_via_ext_ec(void) -{ - uint32_t id = BOARD_ID_INIT; - - if (google_chromeec_get_board_version(&id)) - id = BOARD_ID_UNKNOWN; - - return id; -} - -/* Get Board ID via EC I/O port write/read */ -int get_board_id(void) -{ - MAYBE_STATIC_NONZERO int id = -1; - - if (id < 0) { - if (CONFIG(EC_GOOGLE_CHROMEEC)) - id = get_board_id_via_ext_ec(); - else{ - uint8_t buffer[2]; - uint8_t index; - if (send_ec_command(EC_FAB_ID_CMD) == 0) { - for (index = 0; index < sizeof(buffer); index++) - buffer[index] = recv_ec_data(); - id = (buffer[0] << 8) | buffer[1]; - } - } - } - - return id; -} diff --git a/src/mainboard/intel/icelake_rvp/board_id.h b/src/mainboard/intel/icelake_rvp/board_id.h deleted file mode 100644 index 46314755a1..0000000000 --- a/src/mainboard/intel/icelake_rvp/board_id.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _MAINBOARD_BOARD_ID_H_ -#define _MAINBOARD_BOARD_ID_H_ - -/* Board/FAB ID Command */ -#define EC_FAB_ID_CMD 0x0D - -/* - * Returns board information (board id[15:8] and - * Fab info[7:0]) on success and < 0 on error - */ -int get_board_id(void); - -#endif /* _MAINBOARD_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/icelake_rvp/board_info.txt b/src/mainboard/intel/icelake_rvp/board_info.txt deleted file mode 100644 index 48ec997d1b..0000000000 --- a/src/mainboard/intel/icelake_rvp/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Vendor name: Intel -Board name: Icelake rvp -Category: eval -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/intel/icelake_rvp/bootblock.c b/src/mainboard/intel/icelake_rvp/bootblock.c deleted file mode 100644 index d7f3255974..0000000000 --- a/src/mainboard/intel/icelake_rvp/bootblock.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <bootblock_common.h> -#include <soc/gpio.h> - -void bootblock_mainboard_early_init(void) -{ - const struct pad_config *pads; - size_t num; - - pads = variant_early_gpio_table(&num); - gpio_configure_pads(pads, num); -} diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c deleted file mode 100644 index f848234087..0000000000 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <bootmode.h> -#include <boot/coreboot_tables.h> -#include <gpio.h> -#include <types.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} - -int get_lid_switch(void) -{ - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - return 0; -} - -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} diff --git a/src/mainboard/intel/icelake_rvp/chromeos.fmd b/src/mainboard/intel/icelake_rvp/chromeos.fmd deleted file mode 100644 index f4db8b4bc7..0000000000 --- a/src/mainboard/intel/icelake_rvp/chromeos.fmd +++ /dev/null @@ -1,44 +0,0 @@ -FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x3F0000 { - SI_DESC@0x0 0x1000 - SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x36F000 - } - SI_BIOS@0x400000 0xC00000 { - RW_SECTION_A@0x0 0x2d0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 - } - RW_SECTION_B@0x2d0000 0x2d0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 - } - RW_MISC@0x5a0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - } - RW_ELOG(PRESERVE)@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 - } - SMMSTORE(PRESERVE)@0x5d0000 0x40000 - RW_LEGACY(CBFS)@0x610000 0x1c0000 - WP_RO@0x7d0000 0x430000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x42c000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x33c000 - } - } - } -} diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl deleted file mode 100644 index 5a53226d25..0000000000 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <baseboard/ec.h> -#include <baseboard/gpio.h> - -DefinitionBlock( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 -) -{ - #include <acpi/dsdt_top.asl> - #include <soc/intel/common/block/acpi/acpi/platform.asl> - - // global NVS and variables - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> - - // CPU - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/icelake/acpi/southbridge.asl> - } - } - -#if CONFIG(EC_GOOGLE_CHROMEEC) - /* ChromeOS Embedded Controller */ - Scope (\_SB.PCI0.LPCB) - { - /* ACPI code for EC SuperIO functions */ - #include <ec/google/chromeec/acpi/superio.asl> - /* ACPI code for EC functions */ - #include <ec/google/chromeec/acpi/ec.asl> - } -#endif - - #include <southbridge/intel/common/acpi/sleepstates.asl> -} diff --git a/src/mainboard/intel/icelake_rvp/hda_verb.c b/src/mainboard/intel/icelake_rvp/hda_verb.c deleted file mode 100644 index 79f9a1fcce..0000000000 --- a/src/mainboard/intel/icelake_rvp/hda_verb.c +++ /dev/null @@ -1,2 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/hda_verb.h> diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c deleted file mode 100644 index beb5b590c2..0000000000 --- a/src/mainboard/intel/icelake_rvp/mainboard.c +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <device/device.h> -#include <soc/gpio.h> - -static void mainboard_init(void *chip_info) -{ - const struct pad_config *pads; - size_t num; - - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); -} - -struct chip_operations mainboard_ops = { - .init = mainboard_init, -}; diff --git a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c deleted file mode 100644 index 160f0a53ff..0000000000 --- a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <fsp/api.h> -#include <soc/romstage.h> -#include <spd_bin.h> -#include "board_id.h" -#include "spd/spd.h" - -void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - u8 spd_index = (get_board_id() & 0x1F) & 0x7; - printk(BIOS_DEBUG, "spd index is 0x%x\n", spd_index); - - if (spd_index > 0 && spd_index != 2) { - mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; - - /* Memory leak is ok since we have memory mapped boot media */ - mem_cfg->MemorySpdPtr00 = spd_cbfs_map(spd_index); - if (!mem_cfg->MemorySpdPtr00) - die("spd.bin not found\n"); - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - - mem_cfg->SpdAddressTable[0] = 0x0; - mem_cfg->SpdAddressTable[1] = 0x0; - mem_cfg->SpdAddressTable[2] = 0x0; - mem_cfg->SpdAddressTable[3] = 0x0; - } else { - mem_cfg->MemorySpdPtr00 = 0; - mem_cfg->MemorySpdPtr01 = 0; - mem_cfg->MemorySpdPtr10 = 0; - mem_cfg->MemorySpdPtr11 = 0; - - mem_cfg->SpdAddressTable[0] = 0xA0; - mem_cfg->SpdAddressTable[1] = 0xA2; - mem_cfg->SpdAddressTable[2] = 0xA4; - mem_cfg->SpdAddressTable[3] = 0xA6; - } - mem_cfg->DqPinsInterleaved = 0; - mem_cfg->CaVrefConfig = 0x2; /* VREF_CA->CHA/CHB */ - mem_cfg->ECT = 1; /* Early Command Training Enabled */ - mem_cfg->RefClk = 0; /* Auto Select CLK freq */ - - mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0); - mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1); - mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0); - mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); - mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); -} diff --git a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc b/src/mainboard/intel/icelake_rvp/spd/Makefile.inc deleted file mode 100644 index 8e3ce25085..0000000000 --- a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -romstage-y += spd_util.c - -SPD_SOURCES = empty # 0b000 -SPD_SOURCES += samsung_K4F6E304HBMGCJ # 1b001 -SPD_SOURCES += empty # 2b010 -SPD_SOURCES += empty # 3b011 -SPD_SOURCES += samsung_K4F6E304HBMGCJ # 4b100 -SPD_SOURCES += empty # 5b101 -SPD_SOURCES += samsung_K4F6E304HBMGCJ # 6b110 -SPD_SOURCES += empty # 7b111 diff --git a/src/mainboard/intel/icelake_rvp/spd/empty.spd.hex b/src/mainboard/intel/icelake_rvp/spd/empty.spd.hex deleted file mode 100644 index 67b46cd239..0000000000 --- a/src/mainboard/intel/icelake_rvp/spd/empty.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex b/src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex deleted file mode 100644 index 62dff16182..0000000000 --- a/src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 10 0E 15 19 94 08 00 40 00 00 0A 22 00 00 -00 00 05 0F 92 54 01 00 8A 00 90 A8 90 A0 05 D0 -02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 92 00 A7 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/icelake_rvp/spd/spd.h b/src/mainboard/intel/icelake_rvp/spd/spd.h deleted file mode 100644 index 978f01daa5..0000000000 --- a/src/mainboard/intel/icelake_rvp/spd/spd.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -void mainboard_fill_dq_map_ch0(void *dq_map_ptr); -void mainboard_fill_dq_map_ch1(void *dq_map_ptr); -void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); -void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); -void mainboard_fill_rcomp_res_data(void *rcomp_ptr); -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); -#endif diff --git a/src/mainboard/intel/icelake_rvp/spd/spd_util.c b/src/mainboard/intel/icelake_rvp/spd/spd_util.c deleted file mode 100644 index 39dd65a730..0000000000 --- a/src/mainboard/intel/icelake_rvp/spd/spd_util.c +++ /dev/null @@ -1,129 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cpu/cpu.h> -#include <intelblocks/mp_init.h> -#include <stdint.h> -#include <string.h> - -#include "../board_id.h" -#include "spd.h" - -enum icl_dimm_type { - icl_u_ddr4 = 0, - icl_u_lpddr4 = 1, - icl_u_lpddr4_type_3 = 4, - icl_y_lpddr4 = 6 -}; - -void mainboard_fill_dq_map_ch0(void *dq_map_ptr) -{ - /* DQ byte map Ch0 */ - const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -void mainboard_fill_dq_map_ch1(void *dq_map_ptr) -{ - const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -static uint8_t get_spd_index(void) -{ - uint8_t spd_index = (get_board_id() & 0x1F) & 0x7; - - return spd_index; -} - -void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map Ch0 */ - const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 }; - const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 }; - const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 }; - const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; - - switch (get_spd_index()) { - case icl_u_ddr4: - memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); - break; - case icl_u_lpddr4: - memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); - break; - case icl_u_lpddr4_type_3: - memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3, - sizeof(dqs_map_u_lpddr_type_3)); - break; - case icl_y_lpddr4: - memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); - break; - default: - break; - } -} - -void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map Ch1 */ - const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 }; - const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6 }; - const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 }; - - switch (get_spd_index()) { - case icl_u_ddr4: - memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); - break; - case icl_u_lpddr4: - case icl_u_lpddr4_type_3: - memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); - break; - case icl_y_lpddr4: - memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); - break; - default: - break; - } -} - -void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 100, 100, 100 }; - memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); -} - -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - /* Rcomp target */ - static const u16 RcompTarget_DDR4[5] = { - 100, 33, 32, 33, 28 }; - static const u16 RcompTarget_LPDDR4_Ax[5] = { - 80, 40, 40, 40, 30 }; - static const u16 RcompTarget_LPDDR4_Bx[5] = { - 60, 20, 20, 20, 20 }; - - switch (get_spd_index()) { - case icl_u_ddr4: - memcpy(rcomp_strength_ptr, RcompTarget_DDR4, - sizeof(RcompTarget_DDR4)); - break; - case icl_y_lpddr4: - case icl_u_lpddr4: - case icl_u_lpddr4_type_3: - if (cpu_get_cpuid() == CPUID_ICELAKE_A0) - memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax, - sizeof(RcompTarget_LPDDR4_Ax)); - else - memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Bx, - sizeof(RcompTarget_LPDDR4_Bx)); - break; - default: - break; - } -} diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h deleted file mode 100644 index f05cb7722a..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_EC_H__ -#define __BASEBOARD_EC_H__ - -#include <ec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#include <baseboard/gpio.h> - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) - -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* - * EC can wake from S3 with lid or power button or key press or - * mode change event. - */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -/* - * ACPI related definitions for ASL code. - */ - -/* Enable EC backed ALS device in ACPI */ -#define EC_ENABLE_ALS_DEVICE - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -/* Enable LID switch and provide wake pin for EC */ -#define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ -#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ - -#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h deleted file mode 100644 index de0adf6cff..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_GPIO_H__ -#define __BASEBOARD_GPIO_H__ - -#include <soc/gpe.h> -#include <soc/gpio.h> - -/* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI - -/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ -#define GPE_EC_WAKE GPE0_LAN_WAK - -#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h deleted file mode 100644 index 7233250105..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h +++ /dev/null @@ -1,687 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef HDA_VERB_H -#define HDA_VERB_H - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* ALC 700 */ - 0x10EC0700, - 0xFFFFFFFF, - 0x00000023, - - AZALIA_SUBVENDOR(0, 0x10EC10F2), - AZALIA_PIN_CFG(0, 0x01, 0x00000000), - AZALIA_PIN_CFG(0, 0x12, 0x40000000), - AZALIA_PIN_CFG(0, 0x13, 0x40000000), - AZALIA_PIN_CFG(0, 0x14, 0x411111F0), - AZALIA_PIN_CFG(0, 0x15, 0x411111F0), - AZALIA_PIN_CFG(0, 0x16, 0x411111F0), - AZALIA_PIN_CFG(0, 0x17, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111F0), - AZALIA_PIN_CFG(0, 0x19, 0x04A11030), - AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1D, 0x40622005), - AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1F, 0x411111F0), - AZALIA_PIN_CFG(0, 0x21, 0x04211020), - AZALIA_PIN_CFG(0, 0x29, 0x411111F0), - - /* Widget node 0x20 */ - 0x02050045, - 0x02045289, - 0x0205004A, - 0x0204201B, - /* Widget node 0x20 - 1 */ - 0x05850000, - 0x05843888, - 0x0205006F, - 0x02042C0B, - - //Widget node 0X20 for ALC1305 20160603 update - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040000, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040004, - 0x02050028, - 0x02040600, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FFD0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040080, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040880, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003A, - 0x02050028, - 0x02040DFE, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x0204005D, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x02040442, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040005, - 0x02050028, - 0x02040880, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040006, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040008, - 0x02050028, - 0x0204B000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204002E, - 0x02050028, - 0x02040800, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400C3, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204D4A0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400CC, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204400A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400C1, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x02040320, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040039, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003B, - 0x02050028, - 0x0204FFFF, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FC20, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003A, - 0x02050028, - 0x02041DFE, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C0, - 0x02050028, - 0x020401FA, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C1, - 0x02050028, - 0x0204DE23, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C2, - 0x02050028, - 0x02041C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C3, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C4, - 0x02050028, - 0x02040200, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C5, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C6, - 0x02050028, - 0x020403F5, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C7, - 0x02050028, - 0x0204AF1B, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C8, - 0x02050028, - 0x02041E0A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C9, - 0x02050028, - 0x0204368E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CA, - 0x02050028, - 0x020401FA, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CB, - 0x02050028, - 0x0204DE23, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CC, - 0x02050028, - 0x02041C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CD, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CE, - 0x02050028, - 0x02040200, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CF, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D0, - 0x02050028, - 0x020403F5, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D1, - 0x02050028, - 0x0204AF1B, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D2, - 0x02050028, - 0x02041E0A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D3, - 0x02050028, - 0x0204368E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040040, - 0x02050028, - 0x0204800F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040062, - 0x02050028, - 0x02048000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040063, - 0x02050028, - 0x02044848, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040064, - 0x02050028, - 0x02040800, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040065, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040066, - 0x02050028, - 0x02044004, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040067, - 0x02050028, - 0x02040802, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040068, - 0x02050028, - 0x0204890F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040069, - 0x02050028, - 0x0204E021, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040070, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040071, - 0x02050000, - 0x02043330, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040072, - 0x02050000, - 0x02043333, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040073, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040074, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040075, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040076, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040050, - 0x02050028, - 0x020402EC, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040051, - 0x02050028, - 0x02044909, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040052, - 0x02050028, - 0x020440B0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040046, - 0x02050028, - 0x0204C22E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040047, - 0x02050028, - 0x02040C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040048, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040049, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204004A, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204004B, - 0x02050028, - 0x02041C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x02040090, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204721F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204009E, - 0x02050028, - 0x02040001, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040004, - 0x02050028, - 0x02040500, - 0x02050029, - 0x0204B024 -}; - -const u32 pc_beep_verbs[] = { -}; -AZALIA_ARRAY_SIZES; -#endif diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h deleted file mode 100644 index 48d6c1c738..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_VARIANTS_H__ -#define __BASEBOARD_VARIANTS_H__ - -#include <soc/gpio.h> - -/* The next set of functions return the gpio table and fill in the number of - * entries for each table. */ - -const struct pad_config *variant_gpio_table(size_t *num); -const struct pad_config *variant_early_gpio_table(size_t *num); - -#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc b/src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc deleted file mode 100644 index 9f8b7815b5..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += gpio.c - -ramstage-y += gpio.c diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb deleted file mode 100644 index c00502a258..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ /dev/null @@ -1,345 +0,0 @@ -chip soc/intel/icelake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "SdCardPowerEnableActiveHigh" = "1" - - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 - register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port1 - register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port2 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - - # Enable Pch iSCLK - register "pch_isclk" = "1" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" - - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" - - register "PcieClkSrcUsage[0]" = "2" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "0xC" - register "PcieClkSrcUsage[3]" = "0x70" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "0xE" - register "PcieClkSrcUsage[6]" = "0x80" - register "PcieClkSrcUsage[7]" = "0x80" - register "PcieClkSrcUsage[8]" = "0x80" - register "PcieClkSrcUsage[9]" = "0x80" - register "PcieClkSrcUsage[10]" = "0x80" - register "PcieClkSrcUsage[11]" = "0x80" - register "PcieClkSrcUsage[12]" = "0x80" - register "PcieClkSrcUsage[13]" = "0x80" - register "PcieClkSrcUsage[14]" = "0x80" - register "PcieClkSrcUsage[15]" = "0x80" - - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieClkSrcClkReq[6]" = "6" - register "PcieClkSrcClkReq[7]" = "7" - register "PcieClkSrcClkReq[8]" = "8" - register "PcieClkSrcClkReq[9]" = "9" - register "PcieClkSrcClkReq[10]" = "10" - register "PcieClkSrcClkReq[11]" = "11" - register "PcieClkSrcClkReq[12]" = "12" - register "PcieClkSrcClkReq[13]" = "13" - register "PcieClkSrcClkReq[14]" = "14" - register "PcieClkSrcClkReq[15]" = "15" - - register "SataEnable" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsEnable[3]" = "1" - register "SataPortsEnable[4]" = "1" - register "SataPortsEnable[5]" = "1" - register "SataPortsEnable[6]" = "1" - register "SataPortsEnable[7]" = "1" - - register "SataPortsDevSlp[0]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsDevSlp[2]" = "1" - register "SataPortsDevSlp[3]" = "1" - register "SataPortsDevSlp[4]" = "1" - register "SataPortsDevSlp[5]" = "1" - register "SataPortsDevSlp[6]" = "1" - register "SataPortsDevSlp[7]" = "1" - - register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - }" - - register "SerialIoGSpiMode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI1] = PchSerialIoPci, - [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, - }" - - register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 1, - [PchSerialIoIndexGSPI1] = 1, - [PchSerialIoIndexGSPI2] = 1, - }" - - register "SerialIoGSpiCsState" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, - [PchSerialIoIndexGSPI2] = 0, - }" - - register "SerialIoUartMode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoDisabled, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoSkipInit, - }" - - # Enable DPTF - register "dptf_enable" = "1" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - # Enable S0ix - register "s0ix_enable" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI1 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #+-------------------+---------------------------+ - - register "common_soc_config" = "{ - .gspi[1] = { - .speed_mhz = 1, - .early_init = 1, - }, - }" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 12.0 off end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Lower"" - register "type" = "UPC_TYPE_A" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 2"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 3"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.5 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 4"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.6 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Upper"" - register "type" = "UPC_TYPE_A" - device usb 2.7 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Right Lower"" - register "type" = "UPC_TYPE_A" - device usb 2.8 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Right Upper"" - register "type" = "UPC_TYPE_A" - device usb 2.9 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Lower"" - register "type" = "UPC_TYPE_A" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Upper"" - register "type" = "UPC_TYPE_A" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""WLAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused1"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused2"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused3"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 off end # PMC SRAM - device pci 14.3 on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end # CNVi wifi - device pci 14.5 on end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ALPS0000"" - register "generic.desc" = ""Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)" - register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end - end - end # I2C 0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on - chip drivers/wifi/generic - register "wake" = "GPE0_PCI_EXP" - device pci 00.0 on end - end - end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 on - chip drivers/spi/acpi - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""google,cr50"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - device spi 0 on end - end - end # GSPI #1 - device pci 1f.0 on end # eSPI Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c deleted file mode 100644 index 160f0d3733..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { -/* I2S2_SCLK */ -PAD_CFG_GPI(GPP_A7, NONE, PLTRST), -/* I2S2_RXD */ -PAD_CFG_GPI(GPP_A10, NONE, PLTRST), -/* TCH_PNL2_RST_N */ -PAD_CFG_GPO(GPP_A13, 1, DEEP), -/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */ -PAD_CFG_GPO(GPP_A14, 0, DEEP), -/* TCH_PNL2_INT_N */ -PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST), -/* TC_RETIMER_FORCE_PWR */ -PAD_CFG_GPO(GPP_B4, 0, DEEP), -/* FPS_RST_N */ -PAD_CFG_GPO(GPP_B14, 1, DEEP), -/* WIFI_RF_KILL_N */ -PAD_CFG_GPO(GPP_B15, 1, PLTRST), -/* M2_SSD_PWREN_N */ -PAD_CFG_GPO(GPP_B16, 1, DEEP), -/* WWAN_PERST_N */ -PAD_CFG_GPO(GPP_B17, 1, DEEP), -/* BT_RF_KILL_N */ -PAD_CFG_GPO(GPP_B18, 1, PLTRST), -/* CRD_CAM_PWREN_1 */ -PAD_CFG_GPO(GPP_B23, 1, PLTRST), -/* WF_CAM_CLK_EN */ -PAD_CFG_GPO(GPP_C2, 1, PLTRST), -/* ONBOARD_X4_PCIE_SLOT1_RESET_N */ -PAD_CFG_GPO(GPP_C5, 1, DEEP), -/* TCH_PAD_INT_N */ -PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C8, NONE, PLTRST), -/* WWAN_RST_N */ -PAD_CFG_GPO(GPP_C10, 1, DEEP), -/* WWAN_FCP_OFF_N */ -PAD_CFG_GPO(GPP_C11, 1, DEEP), -/* CODEC_INT_N */ -PAD_CFG_GPI_APIC_LOW(GPP_C12, NONE, PLTRST), -/* SPKR_PD_N */ -PAD_CFG_GPO(GPP_C13, 1, PLTRST), -/* WF_CAM_RST_N */ -PAD_CFG_GPO(GPP_C15, 1, PLTRST), -/* CRD_CAM_STROBE_1 */ -PAD_CFG_GPO(GPP_C22, 0, PLTRST), -/* CRD_CAM_PRIVACY_LED_1 */ -PAD_CFG_GPO(GPP_C23, 0, PLTRST), -/* FLASH_DES_SEC_OVERRIDEs */ -PAD_CFG_GPO(GPP_D13, 0, DEEP), -/* TCH_PAD_LS_EN */ -PAD_CFG_GPO(GPP_D14, 1, PLTRST), -/* ONBOARD_X4_PCIE_SLOT1_DGPU_SEL */ -PAD_CFG_GPO(GPP_D15, 0, DEEP), -/* MFR_MODE_DET_STRAP */ -PAD_CFG_GPI(GPP_D16, NONE, PLTRST), -/* TBT_CIO_PWR_EN */ -PAD_CFG_GPO(GPP_E0, 1, DEEP), -/* FPS_INT */ -PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE), -/* EC_SLP_S0_CS_N */ -PAD_CFG_GPO(GPP_E6, 1, DEEP), -/* EC_SMI_N */ -PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), -/* TBT_CIO_PLUG_EVENT_N */ -PAD_CFG_GPI_SCI(GPP_E17, NONE, DEEP, EDGE_SINGLE, NONE), -/* DISP_AUX_P_BIAS_GPIO */ -PAD_CFG_GPO(GPP_E22, 0, PLTRST), -/* DISP_AUX_N_BIAS_GPIO */ -PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* SATA_HDD_PWREN */ -PAD_CFG_GPO(GPP_F4, 1, PLTRST), -/* BIOS_REC */ -PAD_CFG_GPI(GPP_F5, NONE, PLTRST), -/* SD_CD# */ -PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), -/* SD_WP */ -PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), -/* M2_SSD_RST_N */ -PAD_CFG_GPO(GPP_H0, 1, DEEP), -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* UART2 RX */ - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - /* UART2 TX */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), -}; - -const struct pad_config *variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), -}; - -DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc b/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc deleted file mode 100644 index 9f8b7815b5..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += gpio.c - -ramstage-y += gpio.c diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb deleted file mode 100644 index 0d36f13054..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ /dev/null @@ -1,345 +0,0 @@ -chip soc/intel/icelake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "SdCardPowerEnableActiveHigh" = "1" - - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB3/2 Type A port2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # UNUSED - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # UNUSED - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port1 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port2 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - - # Enable Pch iSCLK - register "pch_isclk" = "1" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" - - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" - - register "PcieClkSrcUsage[0]" = "0x80" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "0xC" - register "PcieClkSrcUsage[3]" = "0x70" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "2" - register "PcieClkSrcUsage[6]" = "0x80" - register "PcieClkSrcUsage[7]" = "0x80" - register "PcieClkSrcUsage[8]" = "0x80" - register "PcieClkSrcUsage[9]" = "0x80" - register "PcieClkSrcUsage[10]" = "0x80" - register "PcieClkSrcUsage[11]" = "0x80" - register "PcieClkSrcUsage[12]" = "0x80" - register "PcieClkSrcUsage[13]" = "0x80" - register "PcieClkSrcUsage[14]" = "0x80" - register "PcieClkSrcUsage[15]" = "0x80" - - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieClkSrcClkReq[6]" = "6" - register "PcieClkSrcClkReq[7]" = "7" - register "PcieClkSrcClkReq[8]" = "8" - register "PcieClkSrcClkReq[9]" = "9" - register "PcieClkSrcClkReq[10]" = "10" - register "PcieClkSrcClkReq[11]" = "11" - register "PcieClkSrcClkReq[12]" = "12" - register "PcieClkSrcClkReq[13]" = "13" - register "PcieClkSrcClkReq[14]" = "14" - register "PcieClkSrcClkReq[15]" = "15" - - register "SataEnable" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsEnable[3]" = "1" - register "SataPortsEnable[4]" = "1" - register "SataPortsEnable[5]" = "1" - register "SataPortsEnable[6]" = "1" - register "SataPortsEnable[7]" = "1" - - register "SataPortsDevSlp[0]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsDevSlp[2]" = "1" - register "SataPortsDevSlp[3]" = "1" - register "SataPortsDevSlp[4]" = "1" - register "SataPortsDevSlp[5]" = "1" - register "SataPortsDevSlp[6]" = "1" - register "SataPortsDevSlp[7]" = "1" - - register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - }" - - register "SerialIoGSpiMode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI1] = PchSerialIoPci, - [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, - }" - - register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 1, - [PchSerialIoIndexGSPI1] = 1, - [PchSerialIoIndexGSPI2] = 1, - }" - - register "SerialIoGSpiCsState" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, - [PchSerialIoIndexGSPI2] = 0, - }" - - register "SerialIoUartMode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoDisabled, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoSkipInit, - }" - - # Enable DPTF - register "dptf_enable" = "1" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - # Enable S0ix - register "s0ix_enable" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI1 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #+-------------------+---------------------------+ - - register "common_soc_config" = "{ - .gspi[1] = { - .speed_mhz = 1, - .early_init = 1, - }, - }" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 12.0 off end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB3-2 Type-A Left Lower"" - register "type" = "UPC_TYPE_A" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3-2 Type-A Left Upper"" - register "type" = "UPC_TYPE_A" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 2"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 3"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.5 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Port Unused 1"" - register "type" = "UPC_TYPE_UNUSED" - device usb 2.6 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Port Unused 2"" - register "type" = "UPC_TYPE_UNUSED" - device usb 2.7 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Right Lower"" - register "type" = "UPC_TYPE_A" - device usb 2.8 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Right Upper"" - register "type" = "UPC_TYPE_A" - device usb 2.9 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Lower"" - register "type" = "UPC_TYPE_A" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Upper"" - register "type" = "UPC_TYPE_A" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""WLAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused1"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused2"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused3"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 off end # PMC SRAM - device pci 14.3 on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end # CNVi wifi - device pci 14.5 on end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ALPS0000"" - register "generic.desc" = ""Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)" - register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end - end - end # I2C 0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on - chip drivers/wifi/generic - register "wake" = "GPE0_PCI_EXP" - device pci 00.0 on end - end - end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 on - chip drivers/spi/acpi - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""google,cr50"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - device spi 0 on end - end - end # GSPI #1 - device pci 1f.0 on end # eSPI Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c deleted file mode 100644 index 160f0d3733..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { -/* I2S2_SCLK */ -PAD_CFG_GPI(GPP_A7, NONE, PLTRST), -/* I2S2_RXD */ -PAD_CFG_GPI(GPP_A10, NONE, PLTRST), -/* TCH_PNL2_RST_N */ -PAD_CFG_GPO(GPP_A13, 1, DEEP), -/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */ -PAD_CFG_GPO(GPP_A14, 0, DEEP), -/* TCH_PNL2_INT_N */ -PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST), -/* TC_RETIMER_FORCE_PWR */ -PAD_CFG_GPO(GPP_B4, 0, DEEP), -/* FPS_RST_N */ -PAD_CFG_GPO(GPP_B14, 1, DEEP), -/* WIFI_RF_KILL_N */ -PAD_CFG_GPO(GPP_B15, 1, PLTRST), -/* M2_SSD_PWREN_N */ -PAD_CFG_GPO(GPP_B16, 1, DEEP), -/* WWAN_PERST_N */ -PAD_CFG_GPO(GPP_B17, 1, DEEP), -/* BT_RF_KILL_N */ -PAD_CFG_GPO(GPP_B18, 1, PLTRST), -/* CRD_CAM_PWREN_1 */ -PAD_CFG_GPO(GPP_B23, 1, PLTRST), -/* WF_CAM_CLK_EN */ -PAD_CFG_GPO(GPP_C2, 1, PLTRST), -/* ONBOARD_X4_PCIE_SLOT1_RESET_N */ -PAD_CFG_GPO(GPP_C5, 1, DEEP), -/* TCH_PAD_INT_N */ -PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C8, NONE, PLTRST), -/* WWAN_RST_N */ -PAD_CFG_GPO(GPP_C10, 1, DEEP), -/* WWAN_FCP_OFF_N */ -PAD_CFG_GPO(GPP_C11, 1, DEEP), -/* CODEC_INT_N */ -PAD_CFG_GPI_APIC_LOW(GPP_C12, NONE, PLTRST), -/* SPKR_PD_N */ -PAD_CFG_GPO(GPP_C13, 1, PLTRST), -/* WF_CAM_RST_N */ -PAD_CFG_GPO(GPP_C15, 1, PLTRST), -/* CRD_CAM_STROBE_1 */ -PAD_CFG_GPO(GPP_C22, 0, PLTRST), -/* CRD_CAM_PRIVACY_LED_1 */ -PAD_CFG_GPO(GPP_C23, 0, PLTRST), -/* FLASH_DES_SEC_OVERRIDEs */ -PAD_CFG_GPO(GPP_D13, 0, DEEP), -/* TCH_PAD_LS_EN */ -PAD_CFG_GPO(GPP_D14, 1, PLTRST), -/* ONBOARD_X4_PCIE_SLOT1_DGPU_SEL */ -PAD_CFG_GPO(GPP_D15, 0, DEEP), -/* MFR_MODE_DET_STRAP */ -PAD_CFG_GPI(GPP_D16, NONE, PLTRST), -/* TBT_CIO_PWR_EN */ -PAD_CFG_GPO(GPP_E0, 1, DEEP), -/* FPS_INT */ -PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE), -/* EC_SLP_S0_CS_N */ -PAD_CFG_GPO(GPP_E6, 1, DEEP), -/* EC_SMI_N */ -PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), -/* TBT_CIO_PLUG_EVENT_N */ -PAD_CFG_GPI_SCI(GPP_E17, NONE, DEEP, EDGE_SINGLE, NONE), -/* DISP_AUX_P_BIAS_GPIO */ -PAD_CFG_GPO(GPP_E22, 0, PLTRST), -/* DISP_AUX_N_BIAS_GPIO */ -PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* SATA_HDD_PWREN */ -PAD_CFG_GPO(GPP_F4, 1, PLTRST), -/* BIOS_REC */ -PAD_CFG_GPI(GPP_F5, NONE, PLTRST), -/* SD_CD# */ -PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), -/* SD_WP */ -PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), -/* M2_SSD_RST_N */ -PAD_CFG_GPO(GPP_H0, 1, DEEP), -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* UART2 RX */ - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - /* UART2 TX */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), -}; - -const struct pad_config *variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), -}; - -DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 85d98b6581..5509df22b9 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -30,7 +30,6 @@ static const unsigned short wifi_pci_device_ids[] = { PCI_DID_INTEL_CNL_LP_CNVI_WIFI, PCI_DID_INTEL_CNL_H_CNVI_WIFI, PCI_DID_INTEL_GLK_CNVI_WIFI, - PCI_DID_INTEL_ICL_CNVI_WIFI, PCI_DID_INTEL_JSL_CNVI_WIFI_0, PCI_DID_INTEL_JSL_CNVI_WIFI_1, PCI_DID_INTEL_JSL_CNVI_WIFI_2, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index d8ca0b3a9a..4636b3b609 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -59,8 +59,6 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_COFFEELAKE_B0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_P0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_R0 }, - { X86_VENDOR_INTEL, CPUID_ICELAKE_A0 }, - { X86_VENDOR_INTEL, CPUID_ICELAKE_B0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_A0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_K0_S0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G0 }, diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ad99e1fe6e..d697c84a97 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1312,7 +1312,6 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LWB_CSE0, PCI_DID_INTEL_LWB_CSE0_SUPER, PCI_DID_INTEL_CNP_H_CSE0, - PCI_DID_INTEL_ICL_CSE0, PCI_DID_INTEL_CMP_CSE0, PCI_DID_INTEL_CMP_H_CSE0, PCI_DID_INTEL_TGL_CSE0, diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 03aa4e52ce..0229ee5b6c 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -29,7 +29,6 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_CNP_H_AUDIO, PCI_DID_INTEL_CMP_AUDIO, PCI_DID_INTEL_CMP_H_AUDIO, - PCI_DID_INTEL_ICL_AUDIO, PCI_DID_INTEL_TGL_AUDIO, PCI_DID_INTEL_TGL_H_AUDIO, PCI_DID_INTEL_MCC_AUDIO, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index bc047277fb..14e7597573 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -236,22 +236,6 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_CFL_S_GT2_3, PCI_DID_INTEL_CFL_S_GT2_4, PCI_DID_INTEL_CFL_S_GT2_5, - PCI_DID_INTEL_ICL_GT0_ULT, - PCI_DID_INTEL_ICL_GT0_5_ULT, - PCI_DID_INTEL_ICL_GT1_ULT, - PCI_DID_INTEL_ICL_GT2_ULX_0, - PCI_DID_INTEL_ICL_GT2_ULX_1, - PCI_DID_INTEL_ICL_GT2_ULT_1, - PCI_DID_INTEL_ICL_GT2_ULX_2, - PCI_DID_INTEL_ICL_GT2_ULT_2, - PCI_DID_INTEL_ICL_GT2_ULX_3, - PCI_DID_INTEL_ICL_GT2_ULT_3, - PCI_DID_INTEL_ICL_GT2_ULX_4, - PCI_DID_INTEL_ICL_GT2_ULT_4, - PCI_DID_INTEL_ICL_GT2_ULX_5, - PCI_DID_INTEL_ICL_GT2_ULT_5, - PCI_DID_INTEL_ICL_GT2_ULX_6, - PCI_DID_INTEL_ICL_GT3_ULT, PCI_DID_INTEL_CML_GT1_ULT_1, PCI_DID_INTEL_CML_GT1_ULT_2, PCI_DID_INTEL_CML_GT2_ULT_1, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index ac938eadc7..c70a61e9c8 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -36,7 +36,6 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LWB_AUDIO_SUPER, PCI_DID_INTEL_CNL_AUDIO, PCI_DID_INTEL_CNP_H_AUDIO, - PCI_DID_INTEL_ICL_AUDIO, PCI_DID_INTEL_CMP_AUDIO, PCI_DID_INTEL_CMP_H_AUDIO, PCI_DID_INTEL_BSW_AUDIO, diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index b2c0367a9a..ef5a0c155c 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -246,13 +246,6 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_CNP_H_LPC_QM370, PCI_DID_INTEL_CNP_H_LPC_HM370, PCI_DID_INTEL_CNP_H_LPC_CM246, - PCI_DID_INTEL_ICL_BASE_U_ESPI, - PCI_DID_INTEL_ICL_BASE_Y_ESPI, - PCI_DID_INTEL_ICL_U_PREMIUM_ESPI, - PCI_DID_INTEL_ICL_U_SUPER_U_ESPI, - PCI_DID_INTEL_ICL_U_SUPER_U_ESPI_REV0, - PCI_DID_INTEL_ICL_SUPER_Y_ESPI, - PCI_DID_INTEL_ICL_Y_PREMIUM_ESPI, PCI_DID_INTEL_CMP_SUPER_U_LPC, PCI_DID_INTEL_CMP_PREMIUM_Y_LPC, PCI_DID_INTEL_CMP_PREMIUM_U_LPC, diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index d95e541216..72dee3ee35 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -146,7 +146,6 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LWB_P2SB_SUPER, PCI_DID_INTEL_CNL_P2SB, PCI_DID_INTEL_CNP_H_P2SB, - PCI_DID_INTEL_ICL_P2SB, PCI_DID_INTEL_CMP_P2SB, PCI_DID_INTEL_CMP_H_P2SB, PCI_DID_INTEL_TGL_P2SB, diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 397e2c2bc1..eee02009f1 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -53,7 +53,6 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_CNL_SD, PCI_DID_INTEL_GLK_SD, PCI_DID_INTEL_CNP_H_SD, - PCI_DID_INTEL_ICL_SD, PCI_DID_INTEL_CMP_SD, PCI_DID_INTEL_CMP_H_SD, PCI_DID_INTEL_MCC_SD, diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index bde0f4fb6f..52f012000c 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -39,7 +39,6 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_CRASHLOG_SRAM, PCI_DID_INTEL_APL_SRAM, PCI_DID_INTEL_GLK_SRAM, - PCI_DID_INTEL_ICL_SRAM, PCI_DID_INTEL_CMP_SRAM, PCI_DID_INTEL_CMP_H_SRAM, PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index d9634fa999..aeeff123c9 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -362,10 +362,6 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_CFL_ID_S_S_4, PCI_DID_INTEL_CFL_ID_S_S_6, PCI_DID_INTEL_CFL_ID_S_S_8, - PCI_DID_INTEL_ICL_ID_U, - PCI_DID_INTEL_ICL_ID_U_2_2, - PCI_DID_INTEL_ICL_ID_Y, - PCI_DID_INTEL_ICL_ID_Y_2, PCI_DID_INTEL_CML_ULT, PCI_DID_INTEL_CML_ULT_2_2, PCI_DID_INTEL_CML_ULT_6_2, diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig deleted file mode 100644 index aca73faae9..0000000000 --- a/src/soc/intel/icelake/Kconfig +++ /dev/null @@ -1,205 +0,0 @@ -config SOC_INTEL_ICELAKE - bool - help - Intel Icelake support - -if SOC_INTEL_ICELAKE - -config CPU_SPECIFIC_OPTIONS - def_bool y - select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_X86 - select BOOT_DEVICE_SUPPORTS_WRITES - select CACHE_MRC_SETTINGS - select SET_IA32_FC_LOCK_BIT - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select CPU_SUPPORTS_PM_TIMER_EMULATION - select DISPLAY_FSP_VERSION_INFO - select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 - select FSP_M_XIP - select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 - select GENERIC_GPIO_LIB - select HAVE_FSP_GOP - select HAVE_INTEL_FSP_REPO - select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_SMI_HANDLER - select IDT_IN_EVERY_STAGE - select INTEL_CAR_NEM_ENHANCED - select INTEL_GMA_ACPI - select INTEL_GMA_ADD_VBT if RUN_FSP_GOP - select MP_SERVICES_PPI_V1 - select MRC_SETTINGS_PROTECT - select PARALLEL_MP_AP_WORK - select MICROCODE_BLOB_UNDISCLOSED - select PLATFORM_USES_FSP2_1 - select PMC_GLOBAL_RESET_ENABLE_LOCK - select CPU_INTEL_COMMON - select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_ACPI - select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC - select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT - select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO - select SOC_INTEL_COMMON_BLOCK_CAR - select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG - select SOC_INTEL_COMMON_BLOCK_CNVI - select SOC_INTEL_COMMON_BLOCK_CPU - select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT - select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE - select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 - select SOC_INTEL_COMMON_BLOCK_HDA - select SOC_INTEL_COMMON_BLOCK_SA - select SOC_INTEL_COMMON_BLOCK_SCS - select SOC_INTEL_COMMON_BLOCK_SMM - select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP - select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV - select SOC_INTEL_COMMON_FSP_RESET - select SOC_INTEL_COMMON_PCH_CLIENT - select SOC_INTEL_COMMON_RESET - select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION - select SSE2 - select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_MONOTONIC_TIMER - select UDELAY_TSC - select UDK_2017_BINDING - select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM - select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT - select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE - select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI - -config DISABLE_HECI1_AT_PRE_BOOT - default y if MAINBOARD_HAS_CHROMEOS - select HECI_DISABLE_USING_SMM - -config DCACHE_RAM_BASE - default 0xfef00000 - -config DCACHE_RAM_SIZE - default 0x40000 - help - The size of the cache-as-ram region required during bootblock - and/or romstage. - -config DCACHE_BSP_STACK_SIZE - hex - default 0x20400 - help - The amount of anticipated stack usage in CAR by bootblock and - other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). - -config FSP_TEMP_RAM_SIZE - hex - default 0x10000 - help - The amount of anticipated heap usage in CAR by FSP. - Refer to Platform FSP integration guide document to know - the exact FSP requirement for Heap setup. - -config IFD_CHIPSET - string - default "icl" - -config IED_REGION_SIZE - hex - default 0x400000 - -config HEAP_SIZE - hex - default 0x8000 - -config MAX_ROOT_PORTS - int - default 16 - -config SMM_TSEG_SIZE - hex - default 0x800000 - -config SMM_RESERVED_SIZE - hex - default 0x200000 - -config PCR_BASE_ADDRESS - hex - default 0xfd000000 - help - This option allows you to select MMIO Base Address of sideband bus. - -config ECAM_MMCONF_BASE_ADDRESS - default 0xc0000000 - -config CPU_BCLK_MHZ - int - default 100 - -config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ - int - default 120 - -config CPU_XTAL_HZ - default 38400000 - -config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ - int - default 133 - -config SOC_INTEL_COMMON_BLOCK_GSPI_MAX - int - default 3 - -config SOC_INTEL_I2C_DEV_MAX - int - default 6 - -config SOC_INTEL_UART_DEV_MAX - int - default 3 - -config CONSOLE_UART_BASE_ADDRESS - hex - default 0xfe032000 - depends on INTEL_LPSS_UART_FOR_CONSOLE - -# Clock divider parameters for 115200 baud rate -config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL - hex - default 0x30 - -config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL - hex - default 0xc35 - -config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_VBNV_CMOS - select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH - -config CBFS_SIZE - default 0x200000 - -config FSP_HEADER_PATH - default "3rdparty/fsp/IceLakeFspBinPkg/Include" - -config FSP_FD_PATH - default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd" - -config SOC_INTEL_ICELAKE_DEBUG_CONSENT - int "Debug Consent for ICL" - # USB DBC is more common for developers so make this default to 3 if - # SOC_INTEL_DEBUG_CONSENT=y - default 3 if SOC_INTEL_DEBUG_CONSENT - default 0 - help - This is to control debug interface on SOC. - Setting non-zero value will allow to use DBC or DCI to debug SOC. - PlatformDebugConsent in FspmUpd.h has the details. - - Desired platform debug types are - 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), - 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), - 6:Enable (2-wire DCI OOB), 7:Manual - -endif diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc deleted file mode 100644 index ad26056a0f..0000000000 --- a/src/soc/intel/icelake/Makefile.inc +++ /dev/null @@ -1,51 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_INTEL_ICELAKE),y) - -subdirs-y += romstage -subdirs-y += ../../../cpu/intel/microcode -subdirs-y += ../../../cpu/intel/turbo - -# all (bootblock, verstage, romstage, postcar, ramstage) -all-y += gspi.c -all-y += i2c.c -all-y += pmutil.c -all-y += spi.c -all-y += uart.c - -bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/pch.c -bootblock-y += bootblock/report_platform.c -bootblock-y += espi.c -bootblock-y += gpio.c -bootblock-y += p2sb.c - -romstage-y += espi.c -romstage-y += gpio.c -romstage-y += reset.c - -ramstage-y += acpi.c -ramstage-y += chip.c -ramstage-y += cpu.c -ramstage-y += elog.c -ramstage-y += espi.c -ramstage-y += finalize.c -ramstage-y += fsp_params.c -ramstage-y += gpio.c -ramstage-y += lockdown.c -ramstage-y += p2sb.c -ramstage-y += pmc.c -ramstage-y += reset.c -ramstage-y += systemagent.c -ramstage-y += sd.c -ramstage-y += me.c - -smm-y += gpio.c -smm-y += p2sb.c -smm-y += pmutil.c -smm-y += smihandler.c -smm-y += uart.c - -CPPFLAGS_common += -I$(src)/soc/intel/icelake -CPPFLAGS_common += -I$(src)/soc/intel/icelake/include - -endif diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c deleted file mode 100644 index 978192786b..0000000000 --- a/src/soc/intel/icelake/acpi.c +++ /dev/null @@ -1,182 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> -#include <acpi/acpigen.h> -#include <device/mmio.h> -#include <arch/smp/mpspec.h> -#include <intelblocks/cpulib.h> -#include <intelblocks/pmclib.h> -#include <intelblocks/acpi.h> -#include <soc/cpu.h> -#include <soc/iomap.h> -#include <soc/nvs.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/soc_chip.h> -#include <soc/systemagent.h> - -/* - * List of supported C-states in this processor. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C6_SHORT_LAT, /* 3 */ - C_STATE_C6_LONG_LAT, /* 4 */ - C_STATE_C7_SHORT_LAT, /* 5 */ - C_STATE_C7_LONG_LAT, /* 6 */ - C_STATE_C7S_SHORT_LAT, /* 7 */ - C_STATE_C7S_LONG_LAT, /* 8 */ - C_STATE_C8, /* 9 */ - C_STATE_C9, /* 10 */ - C_STATE_C10, /* 11 */ - NUM_C_STATES -}; - -static const acpi_cstate_t cstate_map[NUM_C_STATES] = { - [C_STATE_C0] = {}, - [C_STATE_C1] = { - .latency = 0, - .power = C1_POWER, - .resource = MWAIT_RES(0, 0), - }, - [C_STATE_C1E] = { - .latency = 0, - .power = C1_POWER, - .resource = MWAIT_RES(0, 1), - }, - [C_STATE_C6_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = C6_POWER, - .resource = MWAIT_RES(2, 0), - }, - [C_STATE_C6_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = C6_POWER, - .resource = MWAIT_RES(2, 1), - }, - [C_STATE_C7_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = C7_POWER, - .resource = MWAIT_RES(3, 0), - }, - [C_STATE_C7_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = C7_POWER, - .resource = MWAIT_RES(3, 1), - }, - [C_STATE_C7S_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = C7_POWER, - .resource = MWAIT_RES(3, 2), - }, - [C_STATE_C7S_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = C7_POWER, - .resource = MWAIT_RES(3, 3), - }, - [C_STATE_C8] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = C8_POWER, - .resource = MWAIT_RES(4, 0), - }, - [C_STATE_C9] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = C9_POWER, - .resource = MWAIT_RES(5, 0), - }, - [C_STATE_C10] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = C10_POWER, - .resource = MWAIT_RES(6, 0), - }, -}; - -static int cstate_set_non_s0ix[] = { - C_STATE_C1E, - C_STATE_C6_LONG_LAT, - C_STATE_C7S_LONG_LAT -}; - -static int cstate_set_s0ix[] = { - C_STATE_C1E, - C_STATE_C7S_LONG_LAT, - C_STATE_C10 -}; - -const acpi_cstate_t *soc_get_cstate_map(size_t *entries) -{ - static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), - ARRAY_SIZE(cstate_set_non_s0ix))]; - int *set; - int i; - - config_t *config = config_of_soc(); - - int is_s0ix_enable = config->s0ix_enable; - - if (is_s0ix_enable) { - *entries = ARRAY_SIZE(cstate_set_s0ix); - set = cstate_set_s0ix; - } else { - *entries = ARRAY_SIZE(cstate_set_non_s0ix); - set = cstate_set_non_s0ix; - } - - for (i = 0; i < *entries; i++) { - map[i] = cstate_map[set[i]]; - map[i].ctype = i + 1; - } - return map; -} - -void soc_power_states_generation(int core_id, int cores_per_package) -{ - config_t *config = config_of_soc(); - - if (config->eist_enable) - /* Generate P-state tables */ - generate_p_state_entries(core_id, cores_per_package); -} - -void soc_fill_fadt(acpi_fadt_t *fadt) -{ - const uint16_t pmbase = ACPI_BASE_ADDRESS; - - config_t *config = config_of_soc(); - - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x0; - - if (config->s0ix_enable) - fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; -} -uint32_t soc_read_sci_irq_select(void) -{ - return read32p(soc_read_pmc_base() + IRQ_REG); -} - -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - config_t *config = config_of_soc(); - - /* Enable DPTF based on mainboard configuration */ - gnvs->dpte = config->dptf_enable; - - /* Set USB2/USB3 wake enable bitmaps. */ - gnvs->u2we = config->usb2_wake_enable_bitmap; - gnvs->u3we = config->usb3_wake_enable_bitmap; -} - -int soc_madt_sci_irq_polarity(int sci) -{ - return MP_IRQ_POLARITY_HIGH; -} diff --git a/src/soc/intel/icelake/acpi/gpio.asl b/src/soc/intel/icelake/acpi/gpio.asl deleted file mode 100644 index 6a8f824929..0000000000 --- a/src/soc/intel/icelake/acpi/gpio.asl +++ /dev/null @@ -1,105 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/intel/common/block/acpi/acpi/gpio_op.asl> -#include <soc/gpio_defs.h> -#include <soc/irq.h> -#include <soc/pcr_ids.h> - -Device (GPIO) -{ - Name (_HID, "INT3455") - Name (_UID, 0) - Name (_DDN, "GPIO Controller") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0, COM0) - Memory32Fixed (ReadWrite, 0, 0, COM1) - Memory32Fixed (ReadWrite, 0, 0, COM2) - Memory32Fixed (ReadWrite, 0, 0, COM4) - Memory32Fixed (ReadWrite, 0, 0, COM5) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - - Method (_CRS, 0, NotSerialized) - { - /* GPIO Community 0 */ - CreateDWordField (^RBUF, ^COM0._BAS, BAS0) - CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - BAS0 = ^^PCRB (PID_GPIOCOM0) - LEN0 = GPIO_BASE_SIZE - - /* GPIO Community 1 */ - CreateDWordField (^RBUF, ^COM1._BAS, BAS1) - CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - BAS1 = ^^PCRB (PID_GPIOCOM1) - LEN1 = GPIO_BASE_SIZE - - /* GPIO Community 2 */ - CreateDWordField (^RBUF, ^COM2._BAS, BAS2) - CreateDWordField (^RBUF, ^COM2._LEN, LEN2) - BAS2 = ^^PCRB (PID_GPIOCOM2) - LEN2 = GPIO_BASE_SIZE - - /* GPIO Community 4 */ - CreateDWordField (^RBUF, ^COM4._BAS, BAS4) - CreateDWordField (^RBUF, ^COM4._LEN, LEN4) - BAS4 = ^^PCRB (PID_GPIOCOM4) - LEN4 = GPIO_BASE_SIZE - - /* GPIO Community 5 */ - CreateDWordField (^RBUF, ^COM5._BAS, BAS5) - CreateDWordField (^RBUF, ^COM5._LEN, LEN5) - BAS5 = ^^PCRB (PID_GPIOCOM5) - LEN5 = GPIO_BASE_SIZE - - Return (RBUF) - } - - Method (_STA, 0, NotSerialized) - { - Return (0xF) - } -} - -/* - * Get GPIO DW0 Address - * Arg0 - GPIO Number - */ -Method (GADD, 1, NotSerialized) -{ - /* GPIO Community 0 */ - If ((Arg0 >= GPP_G0) && (Arg0 <= GPP_A23)) - { - Local0 = PID_GPIOCOM0 - Local1 = Arg0 - GPP_G0 - } - /* GPIO Community 1 */ - If ((Arg0 >= GPP_H0) && (Arg0 <= GPP_F19)) - { - Local0 = PID_GPIOCOM1 - Local1 = Arg0 - GPP_H0 - } - /* GPIO Community 2 */ - If ((Arg0 >= GPD0) && (Arg0 <= GPD11)) - { - Local0 = PID_GPIOCOM2 - Local1 = Arg0 - GPD0 - } - /* GPIO Community 4 */ - If ((Arg0 >= GPP_C0) && (Arg0 <= GPP_E23)) - { - Local0 = PID_GPIOCOM4 - Local1 = Arg0 - GPP_C0 - } - /* GPIO Community 5 */ - If ((Arg0 >= GPP_R0) && (Arg0 <= GPP_S7)) - { - Local0 = PID_GPIOCOM5 - Local1 = Arg0 - GPP_R0 - } - - Local2 = PCRB (Local0) - Local2 += PAD_CFG_BASE - Return (Local2 + (Local1 * 16)) -} diff --git a/src/soc/intel/icelake/acpi/pch_hda.asl b/src/soc/intel/icelake/acpi/pch_hda.asl deleted file mode 100644 index 4941f6a137..0000000000 --- a/src/soc/intel/icelake/acpi/pch_hda.asl +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Audio Controller - Device 31, Function 3 */ - -Device (HDAS) -{ - Name (_ADR, 0x001f0003) - Name (_DDN, "Audio Controller") - Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) - - /* Device is D3 wake capable */ - Name (_S0W, 3) - - /* NHLT Table Address populated from GNVS values */ - Name (NBUF, ResourceTemplate () { - QWordMemory (ResourceConsumer, PosDecode, MinFixed, - MaxFixed, NonCacheable, ReadOnly, - 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) - }) - - /* - * Device Specific Method - * Arg0 - UUID - * Arg1 - Revision - * Arg2 - Function Index - */ - Method (_DSM, 4) - { - If (Arg0 == ^UUID) { - /* - * Function 0: Function Support Query - * Returns a bitmask of functions supported. - */ - If (Arg2 == 0) { - /* - * NHLT Query only supported for revision 1 and - * if NHLT address and length are set in NVS. - */ - If (Arg1 == 1 && NHLA != 0 && NHLL != 0) { - Return (Buffer (1) { 0x03 }) - } Else { - Return (Buffer (1) { 0x01 }) - } - } - - /* - * Function 1: Query NHLT memory address used by - * Intel Offload Engine Driver to discover any non-HDA - * devices that are supported by the DSP. - * - * Returns a pointer to NHLT table in memory. - */ - If (Arg2 == 1) { - CreateQWordField (NBUF, ^NHLT._MIN, NBAS) - CreateQWordField (NBUF, ^NHLT._MAX, NMAS) - CreateQWordField (NBUF, ^NHLT._LEN, NLEN) - - NBAS = NHLA - NMAS = NHLA - NLEN = NHLL - - Return (NBUF) - } - } - - Return (Buffer (1) { 0x00 }) - } -} diff --git a/src/soc/intel/icelake/acpi/pci_irqs.asl b/src/soc/intel/icelake/acpi/pci_irqs.asl deleted file mode 100644 index 2df1c6294a..0000000000 --- a/src/soc/intel/icelake/acpi/pci_irqs.asl +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <soc/irq.h> - -Name (PICP, Package () { - /* PCI Bridge */ - /* cAVS, SMBus, GbE, Nothpeak */ - Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ }, - Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ }, - Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ }, - Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ }, - /* SerialIo and SCS */ - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - /* PCI Express Port 9-16 */ - Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, - Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, - Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, - Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, - /* PCI Express Port 1-8 */ - Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, - Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, - Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, - Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, - /* eMMC */ - Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, - /* SerialIo */ - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - /* SATA controller */ - Package(){0x0017FFFF, 0, 0, SATA_IRQ }, - /* CSME (HECI, IDE-R, Keyboard and Text redirection */ - Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, - Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, - Package(){0x0016FFFF, 2, 0, IDER_IRQ }, - Package(){0x0016FFFF, 3, 0, KT_IRQ }, - /* SerialIo */ - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, OTG, SRAM, CNVi WiFi */ - Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, OTG_IRQ }, - Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, - Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, - /* Integrated Sensor Hub */ - Package(){0x0013FFFF, 0, 0, ISH_IRQ }, - /* Thermal */ - Package(){0x0012FFFF, 0, 0, THERMAL_IRQ }, - /* Host Bridge */ - /* Root Port D1F0 */ - Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ }, - Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ }, - Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ }, - Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ }, - /* SA IGFX Device */ - Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, - /* SA Thermal Device */ - Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, - /* SA IPU Device */ - Package(){0x0005FFFF, 0, 0, IPU_IRQ }, - /* SA GNA Device */ - Package(){0x0008FFFF, 0, 0, GNA_IRQ }, -}) - -Name (PICN, Package () { - /* D31: cAVS, SMBus, GbE, Nothpeak */ - Package () { 0x001FFFFF, 0, 0, 11 }, - Package () { 0x001FFFFF, 1, 0, 10 }, - Package () { 0x001FFFFF, 2, 0, 11 }, - Package () { 0x001FFFFF, 3, 0, 11 }, - /* D30: Can't use PIC*/ - /* D29: PCI Express Port 9-16 */ - Package () { 0x001DFFFF, 0, 0, 11 }, - Package () { 0x001DFFFF, 1, 0, 10 }, - Package () { 0x001DFFFF, 2, 0, 11 }, - Package () { 0x001DFFFF, 3, 0, 11 }, - /* D28: PCI Express Port 1-8 */ - Package () { 0x001CFFFF, 0, 0, 11 }, - Package () { 0x001CFFFF, 1, 0, 10 }, - Package () { 0x001CFFFF, 2, 0, 11 }, - Package () { 0x001CFFFF, 3, 0, 11 }, - /* D26: Can't use PIC*/ - /* D25: Can't use PIC*/ - /* D23: SATA controller */ - Package () { 0x0017FFFF, 0, 0, 11 }, - /* D22: CSME (HECI, IDE-R, KT redirection */ - Package () { 0x0016FFFF, 0, 0, 11 }, - Package () { 0x0016FFFF, 1, 0, 10 }, - Package () { 0x0016FFFF, 2, 0, 11 }, - Package () { 0x0016FFFF, 3, 0, 11 }, - /* D20: xHCI, OTG, SRAM, CNVi WiFi */ - Package () { 0x0014FFFF, 0, 0, 11 }, - Package () { 0x0014FFFF, 1, 0, 10 }, - Package () { 0x0014FFFF, 2, 0, 11 }, - Package () { 0x0014FFFF, 3, 0, 11 }, - /* D18: Can't use PIC*/ - /* P.E.G. Root Port D1F0 */ - Package () { 0x0001FFFF, 0, 0, 11 }, - Package () { 0x0001FFFF, 1, 0, 10 }, - Package () { 0x0001FFFF, 2, 0, 11 }, - Package () { 0x0001FFFF, 3, 0, 11 }, - /* SA IGFX Device */ - Package () { 0x0002FFFF, 0, 0, 11 }, - /* SA Thermal Device */ - Package () { 0x0004FFFF, 0, 0, 11 }, - /* SA IPU Device */ - Package () { 0x0005FFFF, 0, 0, 11 }, - /* SA GNA Device */ - Package () { 0x0008FFFF, 0, 0, 11 }, -}) - -Method (_PRT) -{ - If (PICM) { - Return (^PICP) - } Else { - Return (^PICN) - } -} diff --git a/src/soc/intel/icelake/acpi/pcie.asl b/src/soc/intel/icelake/acpi/pcie.asl deleted file mode 100644 index 9c0933f92c..0000000000 --- a/src/soc/intel/icelake/acpi/pcie.asl +++ /dev/null @@ -1,369 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel PCH PCIe support */ - -Method (IRQM, 1, Serialized) { - - /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ - Name (IQAA, Package () { - Package () { 0x0000ffff, 0, 0, 16 }, - Package () { 0x0000ffff, 1, 0, 17 }, - Package () { 0x0000ffff, 2, 0, 18 }, - Package () { 0x0000ffff, 3, 0, 19 } }) - Name (IQAP, Package () { - Package () { 0x0000ffff, 0, 0, 11 }, - Package () { 0x0000ffff, 1, 0, 10 }, - Package () { 0x0000ffff, 2, 0, 11 }, - Package () { 0x0000ffff, 3, 0, 11 } }) - - /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ - Name (IQBA, Package () { - Package () { 0x0000ffff, 0, 0, 17 }, - Package () { 0x0000ffff, 1, 0, 18 }, - Package () { 0x0000ffff, 2, 0, 19 }, - Package () { 0x0000ffff, 3, 0, 16 } }) - Name (IQBP, Package () { - Package () { 0x0000ffff, 0, 0, 10 }, - Package () { 0x0000ffff, 1, 0, 11 }, - Package () { 0x0000ffff, 2, 0, 11 }, - Package () { 0x0000ffff, 3, 0, 11 } }) - - /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ - Name (IQCA, Package () { - Package () { 0x0000ffff, 0, 0, 18 }, - Package () { 0x0000ffff, 1, 0, 19 }, - Package () { 0x0000ffff, 2, 0, 16 }, - Package () { 0x0000ffff, 3, 0, 17 } }) - Name (IQCP, Package () { - Package () { 0x0000ffff, 0, 0, 11 }, - Package () { 0x0000ffff, 1, 0, 11 }, - Package () { 0x0000ffff, 2, 0, 11 }, - Package () { 0x0000ffff, 3, 0, 10 } }) - - /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ - Name (IQDA, Package () { - Package () { 0x0000ffff, 0, 0, 19 }, - Package () { 0x0000ffff, 1, 0, 16 }, - Package () { 0x0000ffff, 2, 0, 17 }, - Package () { 0x0000ffff, 3, 0, 18 } }) - Name (IQDP, Package () { - Package () { 0x0000ffff, 0, 0, 11 }, - Package () { 0x0000ffff, 1, 0, 11 }, - Package () { 0x0000ffff, 2, 0, 10 }, - Package () { 0x0000ffff, 3, 0, 11 } }) - - Switch (ToInteger (Arg0)) - { - Case (Package () { 1, 5, 9, 13 }) { - If (PICM) { - Return (IQAA) - } Else { - Return (IQAP) - } - } - - Case (Package () { 2, 6, 10, 14 }) { - If (PICM) { - Return (IQBA) - } Else { - Return (IQBP) - } - } - - Case (Package () { 3, 7, 11, 15 }) { - If (PICM) { - Return (IQCA) - } Else { - Return (IQCP) - } - } - - Case (Package () { 4, 8, 12, 16 }) { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - - Default { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - } -} - -Device (RP01) -{ - Name (_ADR, 0x001C0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001C0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001C0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001C0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001C0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001C0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001C0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP13) -{ - Name (_ADR, 0x001D0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP14) -{ - Name (_ADR, 0x001D0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP15) -{ - Name (_ADR, 0x001D0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP16) -{ - Name (_ADR, 0x001D0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} diff --git a/src/soc/intel/icelake/acpi/scs.asl b/src/soc/intel/icelake/acpi/scs.asl deleted file mode 100644 index 8fbbfaf4a2..0000000000 --- a/src/soc/intel/icelake/acpi/scs.asl +++ /dev/null @@ -1,121 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/pcr_ids.h> - -Scope (\_SB.PCI0) { - - /* - * Clear register 0x1C20/0x4820 - * Arg0 - PCR Port ID - */ - Method(SCSC, 1, Serialized) - { - ^PCRA (Arg0, 0x1C20, 0x0) - ^PCRA (Arg0, 0x4820, 0x0) - } - - /* EMMC */ - Device(PEMC) { - Name(_ADR, 0x001A0000) - Name (_DDN, "eMMC Controller") - Name (TEMP, 0) - - OperationRegion(SCSR, PCI_Config, 0x00, 0x100) - Field(SCSR, WordAcc, NoLock, Preserve) { - Offset (0x84), /* PMECTRLSTATUS */ - PMCR, 16, - Offset (0xA2), /* PG_CONFIG */ - , 2, - PGEN, 1, /* PG_ENABLE */ - } - - Method(_INI) { - /* Clear register 0x1C20/0x4820 */ - ^^SCSC (PID_EMMC) - } - - Method(_PS0, 0, Serialized) { - Stall (50) // Sleep 50 us - - PGEN = 0 // Disable PG - - /* Clear register 0x1C20/0x4820 */ - ^^SCSC (PID_EMMC) - - /* Set Power State to D0 */ - PMCR &= 0xFFFC - ^TEMP = PMCR - } - - Method(_PS3, 0, Serialized) { - PGEN = 1 // Enable PG - - /* Set Power State to D3 */ - PMCR |= 3 - ^TEMP = PMCR - } - - Device (CARD) - { - Name (_ADR, 0x00000008) - Method (_RMV, 0, NotSerialized) - { - Return (0) - } - } - } - - /* SD CARD */ - Device (SDXC) - { - Name (_ADR, 0x00140005) - Name (_DDN, "SD Controller") - Name (TEMP, 0) - - OperationRegion (SDPC, PCI_Config, 0x00, 0x100) - Field (SDPC, WordAcc, NoLock, Preserve) - { - Offset (0x84), /* PMECTRLSTATUS */ - PMCR, 16, - Offset (0xA2), /* PG_CONFIG */ - , 2, - PGEN, 1, /* PG_ENABLE */ - } - - Method(_INI) - { - /* Clear register 0x1C20/0x4820 */ - ^^SCSC (PID_SDX) - } - - Method (_PS0, 0, Serialized) - { - PGEN = 0 /* Disable PG */ - - /* Clear register 0x1C20/0x4820 */ - ^^SCSC (PID_SDX) - - /* Set Power State to D0 */ - PMCR &= 0xFFFC - ^TEMP = PMCR - } - - Method (_PS3, 0, Serialized) - { - PGEN = 1 /* Enable PG */ - - /* Set Power State to D3 */ - PMCR |= 3 - ^TEMP = PMCR - } - - Device (CARD) - { - Name (_ADR, 0x00000008) - Method (_RMV, 0, NotSerialized) - { - Return (1) - } - } - } /* Device (SDXC) */ -} diff --git a/src/soc/intel/icelake/acpi/serialio.asl b/src/soc/intel/icelake/acpi/serialio.asl deleted file mode 100644 index e4a675e335..0000000000 --- a/src/soc/intel/icelake/acpi/serialio.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel Serial IO Devices */ - -Device (I2C0) -{ - Name (_ADR, 0x00150000) - Name (_DDN, "Serial IO I2C Controller 0") -} - -Device (I2C1) -{ - Name (_ADR, 0x00150001) - Name (_DDN, "Serial IO I2C Controller 1") -} - -Device (I2C2) -{ - Name (_ADR, 0x00150002) - Name (_DDN, "Serial IO I2C Controller 2") -} - -Device (I2C3) -{ - Name (_ADR, 0x00150003) - Name (_DDN, "Serial IO I2C Controller 3") -} - -Device (I2C4) -{ - Name (_ADR, 0x00190000) - Name (_DDN, "Serial IO I2C Controller 4") -} - -Device (I2C5) -{ - Name (_ADR, 0x00190001) - Name (_DDN, "Serial IO I2C Controller 5") -} - -Device (SPI0) -{ - Name (_ADR, 0x001e0002) - Name (_DDN, "Serial IO SPI Controller 0") -} - -Device (SPI1) -{ - Name (_ADR, 0x001e0003) - Name (_DDN, "Serial IO SPI Controller 1") -} - -Device (SPI2) -{ - Name (_ADR, 0x00120006) - Name (_DDN, "Serial IO SPI Controller 2") -} - -Device (UAR0) -{ - Name (_ADR, 0x001e0000) - Name (_DDN, "Serial IO UART Controller 0") -} - -Device (UAR1) -{ - Name (_ADR, 0x001e0001) - Name (_DDN, "Serial IO UART Controller 1") -} - -Device (UAR2) -{ - Name (_ADR, 0x00190002) - Name (_DDN, "Serial IO UART Controller 2") -} diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl deleted file mode 100644 index 4abea7c6f9..0000000000 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <intelblocks/itss.h> -#include <intelblocks/pcr.h> -#include <soc/itss.h> -#include <soc/pcr_ids.h> - -/* PCI IRQ assignment */ -#include "pci_irqs.asl" - -/* PCR access */ -#include <soc/intel/common/acpi/pcr.asl> - -/* eMMC, SD Card */ -#include "scs.asl" - -/* GPIO controller */ -#include "gpio.asl" - -/* ESPI 0:1f.0 */ -#include <soc/intel/common/block/acpi/acpi/lpc.asl> - -/* PCH HDA */ -#include "pch_hda.asl" - -/* PCIE Ports */ -#include "pcie.asl" - -/* Serial IO */ -#include "serialio.asl" - -/* SMBus 0:1f.4 */ -#include <soc/intel/common/block/acpi/acpi/smbus.asl> - -/* USB XHCI 0:14.0 */ -#include "xhci.asl" - -/* PCI _OSC */ -#include <soc/intel/common/acpi/pci_osc.asl> - -/* GbE 0:1f.6 */ -#include <soc/intel/common/block/acpi/acpi/pch_glan.asl> diff --git a/src/soc/intel/icelake/acpi/xhci.asl b/src/soc/intel/icelake/acpi/xhci.asl deleted file mode 100644 index 73f7906d17..0000000000 --- a/src/soc/intel/icelake/acpi/xhci.asl +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/gpe.h> - -/* XHCI Controller 0:14.0 */ - -Device (XHCI) -{ - Name (_ADR, 0x00140000) - - Name (_PRW, Package () { GPE0_PME_B0, 3 }) - - Name (_S3D, 3) /* D3 supported in S3 */ - Name (_S0W, 3) /* D3 can wake device in S0 */ - Name (_S3W, 3) /* D3 can wake system from S3 */ - - Method (_PS0, 0, Serialized) - { - - } - - Method (_PS3, 0, Serialized) - { - - } - - /* Root Hub for Icelake-LP PCH */ - Device (RHUB) - { - Name (_ADR, 0) - - /* USB2 */ - Device (HS01) { Name (_ADR, 1) } - Device (HS02) { Name (_ADR, 2) } - Device (HS03) { Name (_ADR, 3) } - Device (HS04) { Name (_ADR, 4) } - Device (HS05) { Name (_ADR, 5) } - Device (HS06) { Name (_ADR, 6) } - Device (HS07) { Name (_ADR, 7) } - Device (HS08) { Name (_ADR, 8) } - Device (HS09) { Name (_ADR, 9) } - Device (HS10) { Name (_ADR, 10) } - Device (HS11) { Name (_ADR, 11) } - Device (HS12) { Name (_ADR, 12) } - - /* USBr */ - Device (USR1) { Name (_ADR, 11) } - Device (USR2) { Name (_ADR, 12) } - - /* USB3 */ - Device (SS01) { Name (_ADR, 13) } - Device (SS02) { Name (_ADR, 14) } - Device (SS03) { Name (_ADR, 15) } - Device (SS04) { Name (_ADR, 16) } - Device (SS05) { Name (_ADR, 17) } - Device (SS06) { Name (_ADR, 18) } - } -} diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c deleted file mode 100644 index ef5ada6239..0000000000 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <intelblocks/fast_spi.h> -#include <intelblocks/systemagent.h> -#include <intelblocks/tco.h> -#include <intelblocks/uart.h> -#include <soc/bootblock.h> - -asmlinkage void bootblock_c_entry(uint64_t base_timestamp) -{ - /* Call lib/bootblock.c main */ - bootblock_main_with_basetime(base_timestamp); -} - -void bootblock_soc_early_init(void) -{ - bootblock_systemagent_early_init(); - bootblock_pch_early_init(); - fast_spi_cache_bios_region(); - pch_early_iorange_init(); - if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) - uart_bootblock_init(); -} - -void bootblock_soc_init(void) -{ - report_platform_info(); - bootblock_pch_init(); - - /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); -} diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c deleted file mode 100644 index 53df10503a..0000000000 --- a/src/soc/intel/icelake/bootblock/pch.c +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/mmio.h> -#include <device/device.h> -#include <device/pci_ops.h> -#include <intelblocks/fast_spi.h> -#include <intelblocks/gspi.h> -#include <intelblocks/lpc_lib.h> -#include <intelblocks/p2sb.h> -#include <intelblocks/pcr.h> -#include <intelblocks/pmclib.h> -#include <intelblocks/rtc.h> -#include <soc/bootblock.h> -#include <soc/iomap.h> -#include <soc/p2sb.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/pcr_ids.h> -#include <soc/pm.h> - -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0600 -#define PCR_PSFX_TO_SHDW_BAR0 0 -#define PCR_PSFX_TO_SHDW_BAR1 0x4 -#define PCR_PSFX_TO_SHDW_BAR2 0x8 -#define PCR_PSFX_TO_SHDW_BAR3 0xC -#define PCR_PSFX_TO_SHDW_BAR4 0x10 -#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 -#define PCR_PSFX_T0_SHDW_PCIEN 0x1C - -static void soc_config_pwrmbase(void) -{ - /* - * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register - */ - pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); - - /* Program PWRM Base */ - pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); - - /* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); - - /* Enable PWRM in PMC */ - setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); -} - -void bootblock_pch_early_init(void) -{ - /* - * Perform P2SB configuration before any another controller initialization as the - * controller might want to perform PCR settings. - */ - p2sb_enable_bar(); - p2sb_configure_hpet(); - - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); - - /* - * Enabling PWRM Base for accessing - * Global Reset Cause Register. - */ - soc_config_pwrmbase(); -} - -static void soc_config_acpibase(void) -{ - uint32_t pmc_reg_value; - - pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + - PCR_PSFX_TO_SHDW_BAR4); - - if (pmc_reg_value != 0xFFFFFFFF) { - /* Disable Io Space before changing the address */ - pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + - PCR_PSFX_T0_SHDW_PCIEN, - ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); - /* Program ABASE in PSF3 PMC space BAR4*/ - pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + - PCR_PSFX_TO_SHDW_BAR4, - ACPI_BASE_ADDRESS); - /* Enable IO Space */ - pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + - PCR_PSFX_T0_SHDW_PCIEN, - ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); - } -} - -void pch_early_iorange_init(void) -{ - uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | - LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; - - /* IO Decode Range */ - if (CONFIG(DRIVERS_UART_8250IO)) - lpc_io_setup_comm_a_b(); - - /* IO Decode Enable */ - lpc_enable_fixed_io_ranges(io_enables); - - /* Program generic IO Decode Range */ - pch_enable_lpc(); -} - -void bootblock_pch_init(void) -{ - /* - * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, - * GPE0_STS, GPE0_EN registers. - */ - soc_config_acpibase(); - - /* Set up GPE configuration */ - pmc_gpe_init(); - - enable_rtc_upper_bank(); -} diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c deleted file mode 100644 index 2a1a13b7fb..0000000000 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ /dev/null @@ -1,191 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <cpu/cpu.h> -#include <cpu/intel/cpu_ids.h> -#include <cpu/intel/microcode.h> -#include <cpu/x86/msr.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <soc/bootblock.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <string.h> - -static struct { - u32 cpuid; - const char *name; -} cpu_table[] = { - { CPUID_ICELAKE_A0, "Icelake A0" }, - { CPUID_ICELAKE_B0, "Icelake B0" }, -}; - -static struct { - u16 mchid; - const char *name; -} mch_table[] = { - { PCI_DID_INTEL_ICL_ID_U, "Icelake-U" }, - { PCI_DID_INTEL_ICL_ID_U_2_2, "Icelake-U-2-2" }, - { PCI_DID_INTEL_ICL_ID_Y, "Icelake-Y" }, - { PCI_DID_INTEL_ICL_ID_Y_2, "Icelake-Y-2" }, -}; - -static struct { - u16 espiid; - const char *name; -} pch_table[] = { - { PCI_DID_INTEL_ICL_BASE_U_ESPI, "Icelake-U Base" }, - { PCI_DID_INTEL_ICL_BASE_Y_ESPI, "Icelake-Y Base" }, - { PCI_DID_INTEL_ICL_U_PREMIUM_ESPI, "Icelake-U Premium" }, - { PCI_DID_INTEL_ICL_U_SUPER_U_ESPI, "Icelake-U Super" }, - { PCI_DID_INTEL_ICL_U_SUPER_U_ESPI_REV0, "Icelake-U Super REV0" }, - { PCI_DID_INTEL_ICL_SUPER_Y_ESPI, "Icelake-Y Super" }, - { PCI_DID_INTEL_ICL_Y_PREMIUM_ESPI, "Icelake-Y Premium" }, -}; - -static struct { - u16 igdid; - const char *name; -} igd_table[] = { - { PCI_DID_INTEL_ICL_GT0_ULT, "Icelake ULT GT0" }, - { PCI_DID_INTEL_ICL_GT0_5_ULT, "Icelake ULT GT0.5" }, - { PCI_DID_INTEL_ICL_GT1_ULT, "Icelake U GT1" }, - { PCI_DID_INTEL_ICL_GT2_ULX_0, "Icelake Y GT2" }, - { PCI_DID_INTEL_ICL_GT2_ULX_1, "Icelake Y GT2_1" }, - { PCI_DID_INTEL_ICL_GT2_ULT_1, "Icelake U GT2_1" }, - { PCI_DID_INTEL_ICL_GT2_ULX_2, "Icelake Y GT2_2" }, - { PCI_DID_INTEL_ICL_GT2_ULT_2, "Icelake U GT2_2" }, - { PCI_DID_INTEL_ICL_GT2_ULX_3, "Icelake Y GT2_3" }, - { PCI_DID_INTEL_ICL_GT2_ULT_3, "Icelake U GT2_3" }, - { PCI_DID_INTEL_ICL_GT2_ULX_4, "Icelake Y GT2_4" }, - { PCI_DID_INTEL_ICL_GT2_ULT_4, "Icelake U GT2_4" }, - { PCI_DID_INTEL_ICL_GT2_ULX_5, "Icelake Y GT2_5" }, - { PCI_DID_INTEL_ICL_GT2_ULT_5, "Icelake U GT2_5" }, - { PCI_DID_INTEL_ICL_GT3_ULT, "Icelake U GT3" }, -}; - -static uint8_t get_dev_revision(pci_devfn_t dev) -{ - return pci_read_config8(dev, PCI_REVISION_ID); -} - -static uint16_t get_dev_id(pci_devfn_t dev) -{ - return pci_read_config16(dev, PCI_DEVICE_ID); -} - -static void report_cpu_info(void) -{ - struct cpuid_result cpuidr; - u32 i, index, cpu_id, cpu_feature_flag; - const char cpu_not_found[] = "Platform info not available"; - const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ - int vt, txt, aes; - static const char *const mode[] = {"NOT ", ""}; - const char *cpu_type = "Unknown"; - u32 p[13]; - - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax >= 0x80000004) { - int j = 0; - - for (i = 2; i <= 4; i++) { - cpuidr = cpuid(index + i); - p[j++] = cpuidr.eax; - p[j++] = cpuidr.ebx; - p[j++] = cpuidr.ecx; - p[j++] = cpuidr.edx; - } - p[12] = 0; - cpu_name = (char *)p; - - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ' && strlen(cpu_name) > 0) - cpu_name++; - } - - cpu_id = cpu_get_cpuid(); - - /* Look for string to match the name */ - for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { - if (cpu_table[i].cpuid == cpu_id) { - cpu_type = cpu_table[i].name; - break; - } - } - - printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); - printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, get_current_microcode_rev()); - - cpu_feature_flag = cpu_get_feature_flags_ecx(); - aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; - txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; - vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; - printk(BIOS_DEBUG, - "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", - mode[aes], mode[txt], mode[vt]); -} - -static void report_mch_info(void) -{ - int i; - pci_devfn_t dev = SA_DEV_ROOT; - uint16_t mchid = get_dev_id(dev); - uint8_t mch_revision = get_dev_revision(dev); - const char *mch_type = "Unknown"; - - for (i = 0; i < ARRAY_SIZE(mch_table); i++) { - if (mch_table[i].mchid == mchid) { - mch_type = mch_table[i].name; - break; - } - } - - printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", - mchid, mch_revision, mch_type); -} - -static void report_pch_info(void) -{ - int i; - pci_devfn_t dev = PCH_DEV_ESPI; - uint16_t espiid = get_dev_id(dev); - const char *pch_type = "Unknown"; - - for (i = 0; i < ARRAY_SIZE(pch_table); i++) { - if (pch_table[i].espiid == espiid) { - pch_type = pch_table[i].name; - break; - } - } - printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", - espiid, get_dev_revision(dev), pch_type); -} - -static void report_igd_info(void) -{ - int i; - pci_devfn_t dev = SA_DEV_IGD; - uint16_t igdid = get_dev_id(dev); - const char *igd_type = "Unknown"; - - for (i = 0; i < ARRAY_SIZE(igd_table); i++) { - if (igd_table[i].igdid == igdid) { - igd_type = igd_table[i].name; - break; - } - } - printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", - igdid, get_dev_revision(dev), igd_type); -} - -void report_platform_info(void) -{ - report_cpu_info(); - report_mch_info(); - report_pch_info(); - report_igd_info(); -} diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c deleted file mode 100644 index 5010583070..0000000000 --- a/src/soc/intel/icelake/chip.c +++ /dev/null @@ -1,155 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <fsp/api.h> -#include <fsp/util.h> -#include <intelblocks/acpi.h> -#include <intelblocks/cfg.h> -#include <intelblocks/gpio.h> -#include <intelblocks/itss.h> -#include <intelblocks/systemagent.h> -#include <intelblocks/xdci.h> -#include <soc/intel/common/vbt.h> -#include <soc/itss.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/soc_chip.h> - -#if CONFIG(HAVE_ACPI_TABLES) -const char *soc_acpi_name(const struct device *dev) -{ - if (dev->path.type == DEVICE_PATH_DOMAIN) - return "PCI0"; - - if (dev->path.type != DEVICE_PATH_PCI) - return NULL; - - switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IGD: return "GFX0"; - case PCH_DEVFN_ISH: return "ISHB"; - case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; - case PCH_DEVFN_I2C0: return "I2C0"; - case PCH_DEVFN_I2C1: return "I2C1"; - case PCH_DEVFN_I2C2: return "I2C2"; - case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_CSE: return "CSE1"; - case PCH_DEVFN_CSE_2: return "CSE2"; - case PCH_DEVFN_CSE_IDER: return "CSED"; - case PCH_DEVFN_CSE_KT: return "CSKT"; - case PCH_DEVFN_CSE_3: return "CSE3"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_PCIE1: return "RP01"; - case PCH_DEVFN_PCIE2: return "RP02"; - case PCH_DEVFN_PCIE3: return "RP03"; - case PCH_DEVFN_PCIE4: return "RP04"; - case PCH_DEVFN_PCIE5: return "RP05"; - case PCH_DEVFN_PCIE6: return "RP06"; - case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PCIE13: return "RP13"; - case PCH_DEVFN_PCIE14: return "RP14"; - case PCH_DEVFN_PCIE15: return "RP15"; - case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_PCIE17: return "RP17"; - case PCH_DEVFN_PCIE18: return "RP18"; - case PCH_DEVFN_PCIE19: return "RP19"; - case PCH_DEVFN_PCIE20: return "RP20"; - case PCH_DEVFN_PCIE21: return "RP21"; - case PCH_DEVFN_PCIE22: return "RP22"; - case PCH_DEVFN_PCIE23: return "RP23"; - case PCH_DEVFN_PCIE24: return "RP24"; - case PCH_DEVFN_UART0: return "UAR0"; - case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_GSPI0: return "SPI0"; - case PCH_DEVFN_GSPI1: return "SPI1"; - case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_P2SB: return "P2SB"; - case PCH_DEVFN_PMC: return "PMC_"; - case PCH_DEVFN_HDA: return "HDAS"; - case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_SPI: return "FSPI"; - case PCH_DEVFN_GBE: return "IGBE"; - case PCH_DEVFN_TRACEHUB:return "THUB"; - } - - return NULL; -} -#endif - -/* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ -static void soc_fill_gpio_pm_configuration(void) -{ - uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_soc(); - - if (config->gpio_override_pm) - memcpy(value, config->gpio_pm, sizeof(value)); - else - memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value)); - - gpio_pm_configure(value, TOTAL_GPIO_COMM); -} - -void soc_init_pre_device(void *chip_info) -{ - /* Snapshot the current GPIO IRQ polarities. FSP is setting a - * default policy that doesn't honor boards' requirements. */ - itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - - /* Perform silicon specific init. */ - fsp_silicon_init(); - - /* Display FIRMWARE_VERSION_INFO_HOB */ - fsp_display_fvi_version_hob(); - - /* Restore GPIO IRQ polarities back to previous settings. */ - itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - - soc_fill_gpio_pm_configuration(); -} - -static struct device_operations pci_domain_ops = { - .read_resources = &pci_domain_read_resources, - .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = &soc_acpi_name, - .acpi_fill_ssdt = ssdt_set_above_4g_pci, -#endif -}; - -static struct device_operations cpu_bus_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .acpi_fill_ssdt = generate_cpu_entries, -}; - -static void soc_enable(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) - dev->ops = &pci_domain_ops; - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) - dev->ops = &cpu_bus_ops; - else if (dev->path.type == DEVICE_PATH_GPIO) - block_gpio_enable(dev); -} - -struct chip_operations soc_intel_icelake_ops = { - CHIP_NAME("Intel Icelake") - .enable_dev = &soc_enable, - .init = &soc_init_pre_device, -}; diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h deleted file mode 100644 index 05ec99c0b5..0000000000 --- a/src/soc/intel/icelake/chip.h +++ /dev/null @@ -1,198 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_CHIP_H_ -#define _SOC_CHIP_H_ - -#include <intelblocks/cfg.h> -#include <drivers/i2c/designware/dw_i2c.h> -#include <intelblocks/gpio.h> -#include <intelblocks/gspi.h> -#include <stdint.h> -#include <soc/gpe.h> -#include <soc/gpio.h> -#include <soc/pch.h> -#include <soc/gpio_defs.h> -#include <soc/pci_devs.h> -#include <soc/pmc.h> -#include <soc/serialio.h> -#include <soc/usb.h> - -struct soc_intel_icelake_config { - - /* Common struct containing soc config data required by common code */ - struct soc_intel_common_config common_soc_config; - - /* Gpio group routed to each dword of the GPE0 block. Values are - * of the form GPP_[A:G] or GPD. */ - uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ - uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ - uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ - - /* Generic IO decode ranges */ - uint32_t gen1_dec; - uint32_t gen2_dec; - uint32_t gen3_dec; - uint32_t gen4_dec; - - /* Enable S0iX support */ - int s0ix_enable; - /* Enable DPTF support */ - int dptf_enable; - - /* Deep SX enable for both AC and DC */ - int deep_s3_enable_ac; - int deep_s3_enable_dc; - int deep_s5_enable_ac; - int deep_s5_enable_dc; - - /* Deep Sx Configuration - * DSX_EN_WAKE_PIN - Enable WAKE# pin - * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin - * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ - uint32_t deep_sx_config; - - /* TCC activation offset */ - uint32_t tcc_offset; - - /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. - * When enabled memory will be training at two different frequencies. - * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled */ - enum { - SaGv_Disabled, - SaGv_FixedLow, - SaGv_FixedMid, - SaGv_FixedHigh, - SaGv_Enabled, - } SaGv; - - /* Rank Margin Tool. 1:Enable, 0:Disable */ - uint8_t RMT; - - /* USB related */ - struct usb2_port_config usb2_ports[16]; - struct usb3_port_config usb3_ports[10]; - /* Wake Enable Bitmap for USB2 ports */ - uint16_t usb2_wake_enable_bitmap; - /* Wake Enable Bitmap for USB3 ports */ - uint16_t usb3_wake_enable_bitmap; - - /* SATA related */ - uint8_t SataEnable; - uint8_t SataMode; - uint8_t SataSalpSupport; - uint8_t SataPortsEnable[8]; - uint8_t SataPortsDevSlp[8]; - - /* Audio related */ - uint8_t PchHdaEnable; - uint8_t PchHdaDspEnable; - - /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ - uint8_t PchHdaAudioLinkHda; - uint8_t PchHdaAudioLinkDmic0; - uint8_t PchHdaAudioLinkDmic1; - uint8_t PchHdaAudioLinkSsp0; - uint8_t PchHdaAudioLinkSsp1; - uint8_t PchHdaAudioLinkSsp2; - uint8_t PchHdaAudioLinkSndw1; - uint8_t PchHdaAudioLinkSndw2; - uint8_t PchHdaAudioLinkSndw3; - uint8_t PchHdaAudioLinkSndw4; - - /* PCIe Root Ports */ - uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to PCIe devices. - * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, - * 0xFF: not used */ - uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; - /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to - * clksrc. */ - uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; - - /* SMBus */ - uint8_t SmbusEnable; - - /* eMMC and SD */ - uint8_t ScsEmmcHs400Enabled; - /* Need to update DLL setting to get Emmc running at HS400 speed */ - uint8_t EmmcUseCustomDlls; - uint32_t EmmcTxCmdDelayRegValue; - uint32_t EmmcTxDataDelay1RegValue; - uint32_t EmmcTxDataDelay2RegValue; - uint32_t EmmcRxCmdDataDelay1RegValue; - uint32_t EmmcRxCmdDataDelay2RegValue; - uint32_t EmmcRxStrobeDelayRegValue; - - /* Enable if SD Card Power Enable Signal is Active High */ - uint8_t SdCardPowerEnableActiveHigh; - - /* Heci related */ - uint8_t Heci3Enabled; - - /* Gfx related */ - uint8_t SkipExtGfxScan; - - uint8_t Device4Enable; - - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; - - /* Enable C6 DRAM */ - uint8_t enable_c6dram; - - /* - * SerialIO device mode selection: - * PchSerialIoDisabled, - * PchSerialIoPci, - * PchSerialIoHidden, - * PchSerialIoLegacyUart, - * PchSerialIoSkipInit - */ - uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; - uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; - uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; - /* - * GSPIn Default Chip Select Mode: - * 0:Hardware Mode, - * 1:Software Mode - */ - uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; - /* - * GSPIn Default Chip Select State: - * 0: Low, - * 1: High - */ - uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; - - /* GPIO SD card detect pin */ - unsigned int sdcard_cd_gpio; - - /* Enable Pch iSCLK */ - uint8_t pch_isclk; - - /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ - bool CnviBtAudioOffload; - - /* - * Override GPIO PM configuration: - * 0: Use FSP default GPIO PM program, - * 1: coreboot to override GPIO PM program - */ - uint8_t gpio_override_pm; - - /* - * GPIO PM configuration: 0 to disable, 1 to enable power gating - * Bit 6-7: Reserved - * Bit 5: MISCCFG_GPSIDEDPCGEN - * Bit 4: MISCCFG_GPRCOMPCDLCGEN - * Bit 3: MISCCFG_GPRTCDLCGEN - * Bit 2: MISCCFG_GSXLCGEN - * Bit 1: MISCCFG_GPDPCGEN - * Bit 0: MISCCFG_GPDLCGEN - */ - uint8_t gpio_pm[TOTAL_GPIO_COMM]; -}; - -typedef struct soc_intel_icelake_config config_t; - -#endif diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c deleted file mode 100644 index 37571758cb..0000000000 --- a/src/soc/intel/icelake/cpu.c +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/pci.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/msr.h> -#include <cpu/intel/smm_reloc.h> -#include <cpu/intel/turbo.h> -#include <cpu/intel/common/common.h> -#include <fsp/api.h> -#include <intelblocks/cpulib.h> -#include <intelblocks/mp_init.h> -#include <intelblocks/msr.h> -#include <soc/cpu.h> -#include <soc/msr.h> -#include <soc/pci_devs.h> -#include <soc/soc_chip.h> -#include <types.h> - -bool cpu_soc_is_in_untrusted_mode(void) -{ - msr_t msr; - - msr = rdmsr(MSR_BIOS_DONE); - return !!(msr.lo & ENABLE_IA_UNTRUSTED); -} - -void cpu_soc_bios_done(void) -{ - msr_t msr; - - msr = rdmsr(MSR_BIOS_DONE); - msr.lo |= ENABLE_IA_UNTRUSTED; - wrmsr(MSR_BIOS_DONE, msr); -} - -static void soc_fsp_load(void) -{ - fsps_load(); -} - -static void configure_misc(void) -{ - msr_t msr; - - config_t *conf = config_of_soc(); - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ - msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - wrmsr(IA32_MISC_ENABLE, msr); - - /* Set EIST status */ - cpu_set_eist(conf->eist_enable); - - /* Disable Thermal interrupts */ - msr.lo = 0; - msr.hi = 0; - wrmsr(IA32_THERM_INTERRUPT, msr); - - /* Enable package critical interrupt only */ - msr.lo = 1 << 4; - msr.hi = 0; - wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); - - /* Enable PROCHOT */ - msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ - msr.lo |= (1 << 23); /* Lock it */ - wrmsr(MSR_POWER_CTL, msr); -} - -static void configure_c_states(void) -{ - msr_t msr; - - /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); - - /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); - - /* C-state Interrupt Response Latency Control 3 - package C8 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); - - /* C-state Interrupt Response Latency Control 4 - package C9 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); - - /* C-state Interrupt Response Latency Control 5 - package C10 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); -} - -/* All CPUs including BSP will run the following function. */ -void soc_core_init(struct device *cpu) -{ - /* Clear out pending MCEs */ - /* TODO(adurbin): This should only be done on a cold boot. Also, some - * of these banks are core vs package scope. For now every CPU clears - * every bank. */ - mca_configure(); - - enable_lapic_tpr(); - - /* Configure c-state interrupt response time */ - configure_c_states(); - - /* Configure Enhanced SpeedStep and Thermal Sensors */ - configure_misc(); - - enable_pm_timer_emulation(); - - /* Enable Direct Cache Access */ - configure_dca_cap(); - - /* Set energy policy */ - set_energy_perf_bias(ENERGY_POLICY_NORMAL); - - /* Enable Turbo */ - enable_turbo(); -} - -static void per_cpu_smm_trigger(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); -} - -static void post_mp_init(void) -{ - /* Set Max Ratio */ - cpu_set_max_ratio(); - - /* - * Now that all APs have been relocated as well as the BSP let SMIs - * start flowing. - */ - global_smi_enable(); -} - -static const struct mp_ops mp_ops = { - /* - * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, - * that are set prior to ramstage. - * Real MTRRs programming are being done after resource allocation. - */ - .pre_mp_init = soc_fsp_load, - .get_cpu_count = get_cpu_count, - .get_smm_info = smm_info, - .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_initialize, - .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = smm_relocation_handler, - .post_mp_init = post_mp_init, -}; - -void soc_init_cpus(struct bus *cpu_bus) -{ - /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(cpu_bus, &mp_ops); -} diff --git a/src/soc/intel/icelake/elog.c b/src/soc/intel/icelake/elog.c deleted file mode 100644 index 01f133ac86..0000000000 --- a/src/soc/intel/icelake/elog.c +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootstate.h> -#include <console/console.h> -#include <stdint.h> -#include <elog.h> -#include <intelblocks/pmclib.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> - -static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) -{ - int i; - - gpe0_sts &= gpe0_en; - - for (i = 0; i <= 31; i++) { - if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); - } -} - -static void pch_log_wake_source(const struct chipset_power_state *ps) -{ - /* Power Button */ - if (ps->pm1_sts & PWRBTN_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); - - /* RTC */ - if (ps->pm1_sts & RTC_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - - /* PCI Express (TODO: determine wake device) */ - if (ps->pm1_sts & PCIEXPWAK_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); - - /* PME (TODO: determine wake device) */ - if (ps->gpe0_sts[GPE_STD] & PME_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); - - /* Internal PME (TODO: determine wake device) */ - if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); - - /* SMBUS Wake */ - if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); - - /* Log GPIO events in set 1-3 */ - pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); - pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); - pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64); - /* Treat the STD as an extension of GPIO to obtain visibility. */ - pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); -} - -static void pch_log_power_and_resets(const struct chipset_power_state *ps) -{ - /* Thermal Trip */ - if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) - elog_add_event(ELOG_TYPE_THERM_TRIP); - - /* PWR_FLR Power Failure */ - if (ps->gen_pmcon_a & PWR_FLR) - elog_add_event(ELOG_TYPE_POWER_FAIL); - - /* SUS Well Power Failure */ - if (ps->gen_pmcon_a & SUS_PWR_FLR) - elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); - - /* TCO Timeout */ - if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO2_STS_SECOND_TO) - elog_add_event(ELOG_TYPE_TCO_RESET); - - /* Power Button Override */ - if (ps->pm1_sts & PRBTNOR_STS) - elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); - - /* RTC reset */ - if (ps->gen_pmcon_b & RTC_BATTERY_DEAD) - elog_add_event(ELOG_TYPE_RTC_RESET); - - /* Host Reset Status */ - if (ps->gen_pmcon_a & HOST_RST_STS) - elog_add_event(ELOG_TYPE_SYSTEM_RESET); - - /* ACPI Wake Event */ - if (ps->prev_sleep_state != ACPI_S0) - elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); -} - -static void pch_log_state(void *unused) -{ - struct chipset_power_state *ps = pmc_get_power_state(); - - if (!ps) { - printk(BIOS_ERR, "chipset_power_state not found!\n"); - return; - } - - /* Power and Reset */ - pch_log_power_and_resets(ps); - - /* Wake Sources */ - if (ps->prev_sleep_state > ACPI_S0) - pch_log_wake_source(ps); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL); - -void elog_gsmi_cb_platform_log_wake_source(void) -{ - struct chipset_power_state ps; - pmc_fill_pm_reg_info(&ps); - pch_log_wake_source(&ps); -} diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c deleted file mode 100644 index 5155cb0253..0000000000 --- a/src/soc/intel/icelake/espi.c +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <pc80/isa-dma.h> -#include <pc80/i8259.h> -#include <device/pci_ops.h> -#include <arch/ioapic.h> -#include <intelblocks/itss.h> -#include <intelblocks/lpc_lib.h> -#include <soc/espi.h> -#include <soc/iomap.h> -#include <soc/irq.h> -#include <soc/pci_devs.h> -#include <soc/pcr_ids.h> -#include <soc/soc_chip.h> - -void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) -{ - const config_t *config = config_of_soc(); - - gen_io_dec[0] = config->gen1_dec; - gen_io_dec[1] = config->gen2_dec; - gen_io_dec[2] = config->gen3_dec; - gen_io_dec[3] = config->gen4_dec; -} - -#if ENV_RAMSTAGE -void lpc_soc_init(struct device *dev) -{ - /* Legacy initialization */ - isa_dma_init(); - pch_misc_init(); - - /* Enable CLKRUN_EN for power gating ESPI */ - lpc_enable_pci_clk_cntl(); - - /* Set ESPI Serial IRQ mode */ - if (CONFIG(SERIRQ_CONTINUOUS_MODE)) - lpc_set_serirq_mode(SERIRQ_CONTINUOUS); - else - lpc_set_serirq_mode(SERIRQ_QUIET); - - /* Interrupt configuration */ - pch_enable_ioapic(); - pch_pirq_init(); - setup_i8259(); - i8259_configure_irq_trigger(9, 1); -} - -/* Fill up ESPI IO resource structure inside SoC directory */ -void pch_lpc_soc_fill_io_resources(struct device *dev) -{ - /* - * PMC pci device gets hidden from PCI bus due to Silicon - * policy hence bind ACPI BASE aka ABASE (offset 0x20) with - * ESPI IO resources to ensure that ABASE falls under PCI reserved - * IO memory range. - * - * Note: Don't add any more resource with same offset 0x20 - * under this device space. - */ - pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4, - ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED); -} - -#endif diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c deleted file mode 100644 index eb7ac10f2e..0000000000 --- a/src/soc/intel/icelake/finalize.c +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootstate.h> -#include <commonlib/console/post_codes.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <device/mmio.h> -#include <device/pci.h> -#include <intelblocks/lpc_lib.h> -#include <intelblocks/pcr.h> -#include <intelblocks/pmclib.h> -#include <intelblocks/tco.h> -#include <intelblocks/thermal.h> -#include <soc/p2sb.h> -#include <soc/pci_devs.h> -#include <soc/pcr_ids.h> -#include <soc/pm.h> -#include <soc/smbus.h> -#include <soc/soc_chip.h> -#include <soc/systemagent.h> -#include <spi-generic.h> - -#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ -#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ -#define CAM_CLK_EN (1 << 1) -#define MIPI_CLK (1 << 0) -#define HDPLL_CLK (0 << 0) - -static void pch_enable_isclk(void) -{ - pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); - pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK); -} - -static void pch_handle_sideband(config_t *config) -{ - if (config->pch_isclk) - pch_enable_isclk(); -} - -static void pch_finalize(void) -{ - config_t *config = config_of_soc(); - - /* TCO Lock down */ - tco_lockdown(); - - /* - * Set low maximum temp threshold value used for dynamic thermal sensor - * shutdown consideration. - * - * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the - * thermal sensor when CPU is in a C-state and DTS Temp <= LTT. - */ - pch_thermal_configuration(); - - pch_handle_sideband(config); - - pmc_clear_pmcon_sts(); -} - -static void soc_finalize(void *unused) -{ - printk(BIOS_DEBUG, "Finalizing chipset.\n"); - - pch_finalize(); - apm_control(APM_CNT_FINALIZE); - - /* Indicate finalize step with post code */ - post_code(POST_OS_BOOT); -} - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c deleted file mode 100644 index a247b79d94..0000000000 --- a/src/soc/intel/icelake/fsp_params.c +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <fsp/api.h> -#include <fsp/util.h> -#include <option.h> -#include <intelblocks/lpss.h> -#include <intelblocks/xdci.h> -#include <soc/intel/common/vbt.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/soc_chip.h> -#include <string.h> -#include <types.h> -#include <fsp/ppi/mp_service_ppi.h> - -static void parse_devicetree(FSP_S_CONFIG *params) -{ - const struct soc_intel_icelake_config *config; - config = config_of_soc(); - - for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) - params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; - - for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { - params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; - params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; - params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; - } - - for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) - params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; -} - -/* UPD parameters to be initialized before SiliconInit */ -void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) -{ - int i; - FSP_S_CONFIG *params = &supd->FspsConfig; - - struct soc_intel_icelake_config *config; - config = config_of_soc(); - - /* Parse device tree and enable/disable devices */ - parse_devicetree(params); - - /* Load VBT before devicetree-specific config. */ - params->GraphicsConfigPtr = (uintptr_t)vbt_get(); - - /* Use coreboot MP PPI services if Kconfig is enabled */ - if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) - params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); - - mainboard_silicon_init_params(params); - - params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); - - params->PavpEnable = CONFIG(PAVP); - - /* Unlock upper 8 bytes of RTC RAM */ - params->PchLockDownRtcMemoryLock = 0; - - params->CnviBtAudioOffload = config->CnviBtAudioOffload; - /* SATA */ - params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); - if (params->SataEnable) { - params->SataMode = config->SataMode; - params->SataSalpSupport = config->SataSalpSupport; - memcpy(params->SataPortsEnable, config->SataPortsEnable, - sizeof(params->SataPortsEnable)); - memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, - sizeof(params->SataPortsDevSlp)); - } - - /* Lan */ - params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); - - /* Audio */ - params->PchHdaDspEnable = config->PchHdaDspEnable; - params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda; - params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0; - params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1; - params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0; - params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1; - params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2; - params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1; - params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2; - params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3; - params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4; - - /* disable Legacy PME */ - memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); - - /* Legacy 8254 timer support */ - bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); - params->Enable8254ClockGating = !use_8254; - params->Enable8254ClockGatingOnS3 = !use_8254; - - /* - * Legacy PM ACPI Timer (and TCO Timer) - * This *must* be 1 in any case to keep FSP from - * 1) enabling PM ACPI Timer emulation in uCode. - * 2) disabling the PM ACPI Timer. - * We handle both by ourself! - */ - params->EnableTcoTimer = 1; - - /* S0ix */ - params->PchPmSlpS0Enable = config->s0ix_enable; - - /* USB */ - for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = - config->usb2_ports[i].enable; - params->Usb2PhyPetxiset[i] = - config->usb2_ports[i].pre_emp_bias; - params->Usb2PhyTxiset[i] = - config->usb2_ports[i].tx_bias; - params->Usb2PhyPredeemp[i] = - config->usb2_ports[i].tx_emp_enable; - params->Usb2PhyPehalfbit[i] = - config->usb2_ports[i].pre_emp_bit; - - if (config->usb2_ports[i].enable) - params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; - else - params->Usb2OverCurrentPin[i] = 0xff; - } - - for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { - params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - if (config->usb3_ports[i].enable) { - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; - } else { - params->Usb3OverCurrentPin[i] = 0xff; - } - if (config->usb3_ports[i].tx_de_emp) { - params->Usb3HsioTxDeEmphEnable[i] = 1; - params->Usb3HsioTxDeEmph[i] = - config->usb3_ports[i].tx_de_emp; - } - if (config->usb3_ports[i].tx_downscale_amp) { - params->Usb3HsioTxDownscaleAmpEnable[i] = 1; - params->Usb3HsioTxDownscaleAmp[i] = - config->usb3_ports[i].tx_downscale_amp; - } - } - - params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); - - /* PCI Express */ - for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { - if (config->PcieClkSrcUsage[i] == 0) - config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; - } - memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, - sizeof(config->PcieClkSrcUsage)); - memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, - sizeof(config->PcieClkSrcClkReq)); - - /* eMMC */ - params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC); - if (params->ScsEmmcEnabled) { - params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; - params->EmmcUseCustomDlls = config->EmmcUseCustomDlls; - if (config->EmmcUseCustomDlls == 1) { - params->EmmcTxCmdDelayRegValue = - config->EmmcTxCmdDelayRegValue; - params->EmmcTxDataDelay1RegValue = - config->EmmcTxDataDelay1RegValue; - params->EmmcTxDataDelay2RegValue = - config->EmmcTxDataDelay2RegValue; - params->EmmcRxCmdDataDelay1RegValue = - config->EmmcRxCmdDataDelay1RegValue; - params->EmmcRxCmdDataDelay2RegValue = - config->EmmcRxCmdDataDelay2RegValue; - params->EmmcRxStrobeDelayRegValue = - config->EmmcRxStrobeDelayRegValue; - } - } - - /* SD */ - params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD); - params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh; - - params->Heci3Enabled = config->Heci3Enabled; - params->Device4Enable = config->Device4Enable; -} - -/* Mainboard GPIO Configuration */ -__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -} diff --git a/src/soc/intel/icelake/gpio.c b/src/soc/intel/icelake/gpio.c deleted file mode 100644 index 7febd01b53..0000000000 --- a/src/soc/intel/icelake/gpio.c +++ /dev/null @@ -1,201 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <intelblocks/gpio.h> -#include <intelblocks/pcr.h> -#include <soc/pcr_ids.h> -#include <soc/pmc.h> - -static const struct reset_mapping rst_map[] = { - { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, -}; - -static const struct reset_mapping rst_map_com0[] = { - { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, -}; - -/* - * The GPIO driver for Icelake on Windows/Linux expects 32 GPIOs per pad - * group, regardless of whether or not there is a physical pad for each - * exposed GPIO number. - * - * This results in the OS having a sparse GPIO map, and devices that need - * to export an ACPI GPIO must use the OS expected number. - * - * Not all pins are usable as GPIO and those groups do not have a pad base. - * - * This layout matches the Linux kernel pinctrl map for CNL-LP at: - * linux/drivers/pinctrl/intel/pinctrl-icelake.c - */ -static const struct pad_group icl_community0_groups[] = { - INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 0), /* GPP_G */ - INTEL_GPP_BASE(GPP_G0, GPP_B0, GPP_B23, 32), /* GPP_B */ - INTEL_GPP(GPP_G0, GPIO_RSVD_0, GPIO_RSVD_1), - INTEL_GPP_BASE(GPP_G0, GPP_A0, GPP_A23, 64), /* GPP_A */ -}; - -static const struct pad_group icl_community1_groups[] = { - INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 96), /* GPP_H */ - INTEL_GPP_BASE(GPP_H0, GPP_D0, GPIO_RSVD_2, 128), /* GPP_D */ - INTEL_GPP_BASE(GPP_H0, GPP_F0, GPP_F19, 160), /* GPP_F */ -}; - -/* This community is not visible to the OS */ -static const struct pad_group icl_community2_groups[] = { - INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */ -}; - -static const struct pad_group icl_community4_groups[] = { - INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 224), /* GPP_C */ - INTEL_GPP(GPP_C0, EDP_BKLTEN, MLK_RST_B), /* HVCMOS */ - INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 256), /* GPP_E */ - INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_8), -}; - -static const struct pad_group icl_community5_groups[] = { - INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 288), /* GPP_R */ - INTEL_GPP_BASE(GPP_C0, GPP_S0, GPP_S7, 320), /* GPP_S */ -}; - -static const struct pad_community icl_communities[TOTAL_GPIO_COMM] = { - /* GPP G, B, A */ - [COMM_0] = { - .port = PID_GPIOCOM0, - .first_pad = GPP_G0, - .last_pad = GPP_A23, - .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, - .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_GBA", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map_com0, - .num_reset_vals = ARRAY_SIZE(rst_map_com0), - .groups = icl_community0_groups, - .num_groups = ARRAY_SIZE(icl_community0_groups), - }, - /* GPP H, D, F */ - [COMM_1] = { - .port = PID_GPIOCOM1, - .first_pad = GPP_H0, - .last_pad = GPP_F19, - .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, - .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_HDF", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), - .groups = icl_community1_groups, - .num_groups = ARRAY_SIZE(icl_community1_groups), - }, - /* GPD */ - [COMM_2] = { - .port = PID_GPIOCOM2, - .first_pad = GPD0, - .last_pad = GPD11, - .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, - .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPD", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), - .groups = icl_community2_groups, - .num_groups = ARRAY_SIZE(icl_community2_groups), - }, - /* GPP C, E */ - [COMM_3] = { - .port = PID_GPIOCOM4, - .first_pad = GPP_C0, - .last_pad = GPP_E23, - .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, - .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_CE", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), - .groups = icl_community4_groups, - .num_groups = ARRAY_SIZE(icl_community4_groups), - }, - /* GPP R, S */ - [COMM_4] = { - .port = PID_GPIOCOM5, - .first_pad = GPP_R0, - .last_pad = GPP_S7, - .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, - .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_RS", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), - .groups = icl_community5_groups, - .num_groups = ARRAY_SIZE(icl_community5_groups), - } -}; - -const struct pad_community *soc_gpio_get_community(size_t *num_communities) -{ - *num_communities = ARRAY_SIZE(icl_communities); - return icl_communities; -} - -const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) -{ - static const struct pmc_to_gpio_route routes[] = { - { PMC_GPP_G, GPP_G }, - { PMC_GPP_B, GPP_B }, - { PMC_GPP_A, GPP_A }, - { PMC_GPP_H, GPP_H }, - { PMC_GPP_D, GPP_D }, - { PMC_GPP_F, GPP_F }, - { PMC_GPD, GPD }, - { PMC_GPP_C, GPP_C }, - { PMC_GPP_E, GPP_E }, - { PMC_GPP_R, GPP_R }, - { PMC_GPP_S, GPP_S } - - }; - *num = ARRAY_SIZE(routes); - return routes; -} diff --git a/src/soc/intel/icelake/gspi.c b/src/soc/intel/icelake/gspi.c deleted file mode 100644 index 61ad2608db..0000000000 --- a/src/soc/intel/icelake/gspi.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <intelblocks/gspi.h> -#include <soc/pci_devs.h> - -int gspi_soc_bus_to_devfn(unsigned int gspi_bus) -{ - switch (gspi_bus) { - case 0: - return PCH_DEVFN_GSPI0; - case 1: - return PCH_DEVFN_GSPI1; - case 2: - return PCH_DEVFN_GSPI2; - } - return -1; -} diff --git a/src/soc/intel/icelake/i2c.c b/src/soc/intel/icelake/i2c.c deleted file mode 100644 index c13a1a6099..0000000000 --- a/src/soc/intel/icelake/i2c.c +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <drivers/i2c/designware/dw_i2c.h> -#include <soc/pci_devs.h> - -int dw_i2c_soc_devfn_to_bus(unsigned int devfn) -{ - switch (devfn) { - case PCH_DEVFN_I2C0: - return 0; - case PCH_DEVFN_I2C1: - return 1; - case PCH_DEVFN_I2C2: - return 2; - case PCH_DEVFN_I2C3: - return 3; - case PCH_DEVFN_I2C4: - return 4; - case PCH_DEVFN_I2C5: - return 5; - } - return -1; -} - -int dw_i2c_soc_bus_to_devfn(unsigned int bus) -{ - switch (bus) { - case 0: - return PCH_DEVFN_I2C0; - case 1: - return PCH_DEVFN_I2C1; - case 2: - return PCH_DEVFN_I2C2; - case 3: - return PCH_DEVFN_I2C3; - case 4: - return PCH_DEVFN_I2C4; - case 5: - return PCH_DEVFN_I2C5; - } - return -1; -} diff --git a/src/soc/intel/icelake/include/soc/bootblock.h b/src/soc/intel/icelake/include/soc/bootblock.h deleted file mode 100644 index cdc350f74a..0000000000 --- a/src/soc/intel/icelake/include/soc/bootblock.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ICELAKE_BOOTBLOCK_H_ -#define _SOC_ICELAKE_BOOTBLOCK_H_ - -/* Bootblock pre console init programming */ -void bootblock_pch_early_init(void); - -/* Bootblock post console init programming */ -void bootblock_pch_init(void); -void pch_early_iorange_init(void); -void report_platform_info(void); - -#endif diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h deleted file mode 100644 index 5dc22ded76..0000000000 --- a/src/soc/intel/icelake/include/soc/cpu.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ICELAKE_CPU_H_ -#define _SOC_ICELAKE_CPU_H_ - -#include <intelblocks/msr.h> - -/* Latency times in units of 32768ns */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d - -/* Power in units of mW */ -#define C1_POWER 0x3e8 -#define C6_POWER 0x15e -#define C7_POWER 0xc8 -#define C8_POWER 0xc8 -#define C9_POWER 0xc8 -#define C10_POWER 0xc8 - -#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) -#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ - C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ - (IRTL_1024_NS >> 10)) - -#endif diff --git a/src/soc/intel/icelake/include/soc/espi.h b/src/soc/intel/icelake/include/soc/espi.h deleted file mode 100644 index ec4af4dfac..0000000000 --- a/src/soc/intel/icelake/include/soc/espi.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ICELAKE_ESPI_H_ -#define _SOC_ICELAKE_ESPI_H_ - -#include <stdint.h> - -/* PCI Configuration Space (D31:F0): ESPI */ -#define SCI_IRQ_SEL (7 << 0) -#define SCIS_IRQ9 0 -#define SCIS_IRQ10 1 -#define SCIS_IRQ11 2 -#define SCIS_IRQ20 4 -#define SCIS_IRQ21 5 -#define SCIS_IRQ22 6 -#define SCIS_IRQ23 7 -#define SERIRQ_CNTL 0x64 -#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */ -#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ -#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ -#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */ -#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */ -#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ -#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ -#define LGMR 0x98 /* ESPI Generic Memory Range */ -#define PCCTL 0xE0 /* PCI Clock Control */ -#define CLKRUN_EN (1 << 0) - -#endif diff --git a/src/soc/intel/icelake/include/soc/gpe.h b/src/soc/intel/icelake/include/soc/gpe.h deleted file mode 100644 index 6c08d35588..0000000000 --- a/src/soc/intel/icelake/include/soc/gpe.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_GPE_H_ -#define _SOC_GPE_H_ - -#include <intelpch/gpe.h> - -#endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/icelake/include/soc/gpio.h b/src/soc/intel/icelake/include/soc/gpio.h deleted file mode 100644 index 5d4269d637..0000000000 --- a/src/soc/intel/icelake/include/soc/gpio.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ICELAKE_GPIO_H_ -#define _SOC_ICELAKE_GPIO_H_ - -#include <soc/gpio_defs.h> -#include <intelblocks/gpio.h> - -#define CROS_GPIO_DEVICE_NAME "INT3455:00" - -/* Enable GPIO community power management configuration */ -#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPSIDEDPCGEN | \ - MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \ - | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN) - -#endif diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h deleted file mode 100644 index 1291304384..0000000000 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ /dev/null @@ -1,262 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ICELAKE_GPIO_DEFS_H_ -#define _SOC_ICELAKE_GPIO_DEFS_H_ - -#ifndef __ACPI__ -#include <stddef.h> -#endif -#include <soc/gpio_soc_defs.h> - -#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ - -#define NUM_GPIO_COMx_GPI_REGS(n) \ - (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) - -#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) -#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) -#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) -#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) -#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) - -#define NUM_GPI_STATUS_REGS \ - ((NUM_GPIO_COM0_GPI_REGS) +\ - (NUM_GPIO_COM1_GPI_REGS) +\ - (NUM_GPIO_COM2_GPI_REGS) +\ - (NUM_GPIO_COM4_GPI_REGS) +\ - (NUM_GPIO_COM5_GPI_REGS)) -/* - * IOxAPIC IRQs for the GPIOs - */ - -/* Group G */ -#define GPP_G0_IRQ 0x18 -#define GPP_G1_IRQ 0x19 -#define GPP_G2_IRQ 0x1a -#define GPP_G3_IRQ 0x1b -#define GPP_G4_IRQ 0x1c -#define GPP_G5_IRQ 0x1d -#define GPP_G6_IRQ 0x1e -#define GPP_G7_IRQ 0x1f - -/* Group B */ -#define GPP_B0_IRQ 0x20 -#define GPP_B1_IRQ 0x21 -#define GPP_B2_IRQ 0x22 -#define GPP_B3_IRQ 0x23 -#define GPP_B4_IRQ 0x24 -#define GPP_B5_IRQ 0x25 -#define GPP_B6_IRQ 0x26 -#define GPP_B7_IRQ 0x27 -#define GPP_B8_IRQ 0x28 -#define GPP_B9_IRQ 0x29 -#define GPP_B10_IRQ 0x2a -#define GPP_B11_IRQ 0x2b -#define GPP_B12_IRQ 0x2c -#define GPP_B13_IRQ 0x2d -#define GPP_B14_IRQ 0x2e -#define GPP_B15_IRQ 0x2f -#define GPP_B16_IRQ 0x30 -#define GPP_B17_IRQ 0x31 -#define GPP_B18_IRQ 0x32 -#define GPP_B19_IRQ 0x33 -#define GPP_B20_IRQ 0x34 -#define GPP_B21_IRQ 0x35 -#define GPP_B22_IRQ 0x36 -#define GPP_B23_IRQ 0x37 - -/* Group A */ -#define GPP_A0_IRQ 0x38 -#define GPP_A1_IRQ 0x39 -#define GPP_A2_IRQ 0x3a -#define GPP_A3_IRQ 0x3b -#define GPP_A4_IRQ 0x3c -#define GPP_A5_IRQ 0x3d -#define GPP_A6_IRQ 0x3e -#define GPP_A7_IRQ 0x3f -#define GPP_A8_IRQ 0x40 -#define GPP_A9_IRQ 0x41 -#define GPP_A10_IRQ 0x42 -#define GPP_A11_IRQ 0x43 -#define GPP_A12_IRQ 0x44 -#define GPP_A13_IRQ 0x45 -#define GPP_A14_IRQ 0x46 -#define GPP_A15_IRQ 0x47 -#define GPP_A16_IRQ 0x48 -#define GPP_A17_IRQ 0x49 -#define GPP_A18_IRQ 0x4a -#define GPP_A19_IRQ 0x4b -#define GPP_A20_IRQ 0x4c -#define GPP_A21_IRQ 0x4d -#define GPP_A22_IRQ 0x4e -#define GPP_A23_IRQ 0x4f - -/* Group H */ -#define GPP_H0_IRQ 0x70 -#define GPP_H1_IRQ 0x71 -#define GPP_H2_IRQ 0x72 -#define GPP_H3_IRQ 0x73 -#define GPP_H4_IRQ 0x74 -#define GPP_H5_IRQ 0x75 -#define GPP_H6_IRQ 0x76 -#define GPP_H7_IRQ 0x77 -#define GPP_H8_IRQ 0x18 -#define GPP_H9_IRQ 0x19 -#define GPP_H10_IRQ 0x1a -#define GPP_H11_IRQ 0x1b -#define GPP_H12_IRQ 0x1c -#define GPP_H13_IRQ 0x1d -#define GPP_H14_IRQ 0x1e -#define GPP_H15_IRQ 0x1f -#define GPP_H16_IRQ 0x20 -#define GPP_H17_IRQ 0x21 -#define GPP_H18_IRQ 0x22 -#define GPP_H19_IRQ 0x23 -#define GPP_H20_IRQ 0x24 -#define GPP_H21_IRQ 0x25 -#define GPP_H22_IRQ 0x26 -#define GPP_H23_IRQ 0x27 - -/* Group D */ -#define GPP_D0_IRQ 0x28 -#define GPP_D1_IRQ 0x29 -#define GPP_D2_IRQ 0x2a -#define GPP_D3_IRQ 0x2b -#define GPP_D4_IRQ 0x2c -#define GPP_D5_IRQ 0x2d -#define GPP_D6_IRQ 0x2e -#define GPP_D7_IRQ 0x2f -#define GPP_D8_IRQ 0x30 -#define GPP_D9_IRQ 0x31 -#define GPP_D10_IRQ 0x32 -#define GPP_D11_IRQ 0x33 -#define GPP_D12_IRQ 0x34 -#define GPP_D13_IRQ 0x35 -#define GPP_D14_IRQ 0x36 -#define GPP_D15_IRQ 0x37 -#define GPP_D16_IRQ 0x38 -#define GPP_D17_IRQ 0x39 -#define GPP_D18_IRQ 0x3a -#define GPP_D19_IRQ 0x3b - -/* Group F */ -#define GPP_F0_IRQ 0x40 -#define GPP_F1_IRQ 0x41 -#define GPP_F2_IRQ 0x42 -#define GPP_F3_IRQ 0x43 -#define GPP_F4_IRQ 0x44 -#define GPP_F5_IRQ 0x45 -#define GPP_F6_IRQ 0x46 -#define GPP_F7_IRQ 0x47 -#define GPP_F8_IRQ 0x48 -#define GPP_F9_IRQ 0x49 -#define GPP_F10_IRQ 0x4a -#define GPP_F11_IRQ 0x4b -#define GPP_F12_IRQ 0x4c -#define GPP_F13_IRQ 0x4d -#define GPP_F14_IRQ 0x4e -#define GPP_F15_IRQ 0x4f -#define GPP_F16_IRQ 0x50 -#define GPP_F17_IRQ 0x51 -#define GPP_F18_IRQ 0x52 -#define GPP_F19_IRQ 0x53 - -/* Group GPD */ -#define GPD0_IRQ 0x64 -#define GPD1_IRQ 0x65 -#define GPD2_IRQ 0x66 -#define GPD3_IRQ 0x67 -#define GPD4_IRQ 0x68 -#define GPD5_IRQ 0x69 -#define GPD6_IRQ 0x6a -#define GPD7_IRQ 0x6b -#define GPD8_IRQ 0x6c -#define GPD9_IRQ 0x6d -#define GPD10_IRQ 0x6e -#define GPD11_IRQ 0x6f - -/* Group C */ -#define GPP_C0_IRQ 0x5a -#define GPP_C1_IRQ 0x5b -#define GPP_C2_IRQ 0x5c -#define GPP_C3_IRQ 0x5d -#define GPP_C4_IRQ 0x5e -#define GPP_C5_IRQ 0x5f -#define GPP_C6_IRQ 0x60 -#define GPP_C7_IRQ 0x61 -#define GPP_C8_IRQ 0x62 -#define GPP_C9_IRQ 0x63 -#define GPP_C10_IRQ 0x64 -#define GPP_C11_IRQ 0x65 -#define GPP_C12_IRQ 0x66 -#define GPP_C13_IRQ 0x67 -#define GPP_C14_IRQ 0x68 -#define GPP_C15_IRQ 0x69 -#define GPP_C16_IRQ 0x6a -#define GPP_C17_IRQ 0x6b -#define GPP_C18_IRQ 0x6c -#define GPP_C19_IRQ 0x6d -#define GPP_C20_IRQ 0x6e -#define GPP_C21_IRQ 0x6f -#define GPP_C22_IRQ 0x70 -#define GPP_C23_IRQ 0x71 -/* Group E */ -#define GPP_E0_IRQ 0x72 -#define GPP_E1_IRQ 0x73 -#define GPP_E2_IRQ 0x74 -#define GPP_E3_IRQ 0x75 -#define GPP_E4_IRQ 0x76 -#define GPP_E5_IRQ 0x77 -#define GPP_E6_IRQ 0x18 -#define GPP_E7_IRQ 0x19 -#define GPP_E8_IRQ 0x1a -#define GPP_E9_IRQ 0x1b -#define GPP_E10_IRQ 0x1c -#define GPP_E11_IRQ 0x1d -#define GPP_E12_IRQ 0x1e -#define GPP_E13_IRQ 0x1f -#define GPP_E14_IRQ 0x20 -#define GPP_E15_IRQ 0x21 -#define GPP_E16_IRQ 0x22 -#define GPP_E17_IRQ 0x23 -#define GPP_E18_IRQ 0x24 -#define GPP_E19_IRQ 0x25 -#define GPP_E20_IRQ 0x26 -#define GPP_E21_IRQ 0x27 -#define GPP_E22_IRQ 0x28 -#define GPP_E23_IRQ 0x29 - -/* Group R*/ -#define GPP_R0_IRQ 0x50 -#define GPP_R1_IRQ 0x51 -#define GPP_R2_IRQ 0x52 -#define GPP_R3_IRQ 0x53 -#define GPP_R4_IRQ 0x54 -#define GPP_R5_IRQ 0x55 -#define GPP_R6_IRQ 0x56 -#define GPP_R7_IRQ 0x57 - -/* Group S */ -#define GPP_S0_IRQ 0x5c -#define GPP_S1_IRQ 0x5d -#define GPP_S2_IRQ 0x5e -#define GPP_S3_IRQ 0x5f -#define GPP_S4_IRQ 0x60 -#define GPP_S5_IRQ 0x61 -#define GPP_S6_IRQ 0x62 -#define GPP_S7_IRQ 0x63 - -/* Register defines. */ -#define GPIO_MISCCFG 0x10 -#define GPE_DW_SHIFT 8 -#define GPE_DW_MASK 0xfff00 -#define HOSTSW_OWN_REG_0 0xb0 -#define GPI_INT_STS_0 0x100 -#define GPI_INT_EN_0 0x110 -#define GPI_SMI_STS_0 0x170 -#define GPI_SMI_EN_0 0x190 -#define GPI_NMI_STS_0 0x1b0 -#define GPI_NMI_EN_0 0x1d0 -#define PAD_CFG_BASE 0x600 - -#endif diff --git a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h deleted file mode 100644 index 0e9b4e7a03..0000000000 --- a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h +++ /dev/null @@ -1,284 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ICELAKE_GPIO_SOC_DEFS_H_ -#define _SOC_ICELAKE_GPIO_SOC_DEFS_H_ - -/* - * Most of the fixed numbers and macros are based on the GPP groups. - * The GPIO groups are accessed through register blocks called - * communities. - */ -#define GPP_G 0x0 -#define GPP_B 0x1 -#define GPP_A 0x2 -#define GPP_R 0x3 -#define GPP_S 0x4 -#define GPD 0x5 -#define GPP_H 0x6 -#define GPP_D 0x7 -#define GPP_F 0x8 -#define GPP_VGPIO 0x9 -#define GPP_C 0xA -#define GPP_E 0xB - -#define GPIO_MAX_NUM_PER_GROUP 24 - -/* - * GPIOs are ordered monotonically increasing to match ACPI/OS driver. - */ - -/* Group G */ -#define GPP_G0 0 -#define GPP_G1 1 -#define GPP_G2 2 -#define GPP_G3 3 -#define GPP_G4 4 -#define GPP_G5 5 -#define GPP_G6 6 -#define GPP_G7 7 - -/* Group B */ -#define GPP_B0 8 -#define GPP_B1 9 -#define GPP_B2 10 -#define GPP_B3 11 -#define GPP_B4 12 -#define GPP_B5 13 -#define GPP_B6 14 -#define GPP_B7 15 -#define GPP_B8 16 -#define GPP_B9 17 -#define GPP_B10 18 -#define GPP_B11 19 -#define GPP_B12 20 -#define GPP_B13 21 -#define GPP_B14 22 -#define GPP_B15 23 -#define GPP_B16 24 -#define GPP_B17 25 -#define GPP_B18 26 -#define GPP_B19 27 -#define GPP_B20 28 -#define GPP_B21 29 -#define GPP_B22 30 -#define GPP_B23 31 -#define GPIO_RSVD_0 32 -#define GPIO_RSVD_1 33 - -/* Group A */ -#define GPP_A0 34 -#define GPP_A1 35 -#define GPP_A2 36 -#define GPP_A3 37 -#define GPP_A4 38 -#define GPP_A5 39 -#define GPP_A6 40 -#define GPP_A7 41 -#define GPP_A8 42 -#define GPP_A9 43 -#define GPP_A10 44 -#define GPP_A11 45 -#define GPP_A12 46 -#define GPP_A13 47 -#define GPP_A14 48 -#define GPP_A15 49 -#define GPP_A16 50 -#define GPP_A17 51 -#define GPP_A18 52 -#define GPP_A19 53 -#define GPP_A20 54 -#define GPP_A21 55 -#define GPP_A22 56 -#define GPP_A23 57 - -#define NUM_GPIO_COM0_PADS (GPP_A23 - GPP_G0 + 1) - -/* Group H */ -#define GPP_H0 58 -#define GPP_H1 59 -#define GPP_H2 60 -#define GPP_H3 61 -#define GPP_H4 62 -#define GPP_H5 63 -#define GPP_H6 64 -#define GPP_H7 65 -#define GPP_H8 66 -#define GPP_H9 67 -#define GPP_H10 68 -#define GPP_H11 69 -#define GPP_H12 70 -#define GPP_H13 71 -#define GPP_H14 72 -#define GPP_H15 73 -#define GPP_H16 74 -#define GPP_H17 75 -#define GPP_H18 76 -#define GPP_H19 77 -#define GPP_H20 78 -#define GPP_H21 79 -#define GPP_H22 80 -#define GPP_H23 81 - -/* Group D */ -#define GPP_D0 82 -#define GPP_D1 83 -#define GPP_D2 84 -#define GPP_D3 85 -#define GPP_D4 86 -#define GPP_D5 87 -#define GPP_D6 88 -#define GPP_D7 89 -#define GPP_D8 90 -#define GPP_D9 91 -#define GPP_D10 92 -#define GPP_D11 93 -#define GPP_D12 94 -#define GPP_D13 95 -#define GPP_D14 96 -#define GPP_D15 97 -#define GPP_D16 98 -#define GPP_D17 99 -#define GPP_D18 100 -#define GPP_D19 101 -#define GPIO_RSVD_2 102 - -/* Group F */ -#define GPP_F0 103 -#define GPP_F1 104 -#define GPP_F2 105 -#define GPP_F3 106 -#define GPP_F4 107 -#define GPP_F5 108 -#define GPP_F6 109 -#define GPP_F7 110 -#define GPP_F8 111 -#define GPP_F9 112 -#define GPP_F10 113 -#define GPP_F11 114 -#define GPP_F12 115 -#define GPP_F13 116 -#define GPP_F14 117 -#define GPP_F15 118 -#define GPP_F16 119 -#define GPP_F17 120 -#define GPP_F18 121 -#define GPP_F19 122 - -#define NUM_GPIO_COM1_PADS (GPP_F19 - GPP_H0 + 1) - -/* Group GPD */ -#define GPD0 123 -#define GPD1 124 -#define GPD2 125 -#define GPD3 126 -#define GPD4 127 -#define GPD5 128 -#define GPD6 129 -#define GPD7 130 -#define GPD8 131 -#define GPD9 132 -#define GPD10 133 -#define GPD11 134 - -#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) - -/* Group C */ -#define GPP_C0 135 -#define GPP_C1 136 -#define GPP_C2 137 -#define GPP_C3 138 -#define GPP_C4 139 -#define GPP_C5 140 -#define GPP_C6 141 -#define GPP_C7 142 -#define GPP_C8 143 -#define GPP_C9 144 -#define GPP_C10 145 -#define GPP_C11 146 -#define GPP_C12 147 -#define GPP_C13 148 -#define GPP_C14 149 -#define GPP_C15 150 -#define GPP_C16 151 -#define GPP_C17 152 -#define GPP_C18 153 -#define GPP_C19 154 -#define GPP_C20 155 -#define GPP_C21 156 -#define GPP_C22 157 -#define GPP_C23 158 -#define GPIO_RSVD_3 159 -#define GPIO_RSVD_4 160 -#define GPIO_RSVD_5 161 -#define GPIO_RSVD_6 162 -#define GPIO_RSVD_7 163 -#define GPIO_RSVD_8 164 - -/* Group HVCMOS */ -#define EDP_BKLTEN 165 -#define EDP_BKLTCTL 166 -#define EDP_VDDEN 167 -#define SYS_PWROK 168 -#define SYS_RESET_B 169 -#define MLK_RST_B 170 - -/* Group E */ -#define GPP_E0 171 -#define GPP_E1 172 -#define GPP_E2 173 -#define GPP_E3 174 -#define GPP_E4 175 -#define GPP_E5 176 -#define GPP_E6 177 -#define GPP_E7 178 -#define GPP_E8 179 -#define GPP_E9 180 -#define GPP_E10 181 -#define GPP_E11 182 -#define GPP_E12 183 -#define GPP_E13 184 -#define GPP_E14 185 -#define GPP_E15 186 -#define GPP_E16 187 -#define GPP_E17 188 -#define GPP_E18 189 -#define GPP_E19 190 -#define GPP_E20 191 -#define GPP_E21 192 -#define GPP_E22 193 -#define GPP_E23 194 - -#define NUM_GPIO_COM4_PADS (GPP_E23 - GPP_C0 + 1) - -/* Group R*/ -#define GPP_R0 195 -#define GPP_R1 196 -#define GPP_R2 197 -#define GPP_R3 198 -#define GPP_R4 199 -#define GPP_R5 200 -#define GPP_R6 201 -#define GPP_R7 202 - -/* Group S */ -#define GPP_S0 203 -#define GPP_S1 204 -#define GPP_S2 205 -#define GPP_S3 206 -#define GPP_S4 207 -#define GPP_S5 208 -#define GPP_S6 209 -#define GPP_S7 210 - -#define NUM_GPIO_COM5_PADS (GPP_S7 - GPP_R0 + 1) - -#define TOTAL_PADS 211 - -#define COMM_0 0 -#define COMM_1 1 -#define COMM_2 2 -#define COMM_3 3 -#define COMM_4 4 -#define TOTAL_GPIO_COMM 5 - -#endif diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h deleted file mode 100644 index becb045b8b..0000000000 --- a/src/soc/intel/icelake/include/soc/iomap.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ICELAKE_IOMAP_H_ -#define _SOC_ICELAKE_IOMAP_H_ - -/* - * Memory-mapped I/O registers. - */ -#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 -#define PCH_PRESERVED_BASE_SIZE 0x02000000 - -#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 -#define PCH_TRACE_HUB_BASE_SIZE 0x00800000 - -#define EARLY_I2C_BASE_ADDRESS 0xfe040000 -#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) - -#define MCH_BASE_ADDRESS 0xfed10000 -#define MCH_BASE_SIZE 0x8000 - -#define DMI_BASE_ADDRESS 0xfeda0000 -#define DMI_BASE_SIZE 0x1000 - -#define EP_BASE_ADDRESS 0xfeda1000 -#define EP_BASE_SIZE 0x1000 - -#define EDRAM_BASE_ADDRESS 0xfed80000 -#define EDRAM_BASE_SIZE 0x4000 - -#define REG_BASE_ADDRESS 0xfc000000 -#define REG_BASE_SIZE 0x1000 - -#define PCH_PWRM_BASE_ADDRESS 0xfe000000 -#define PCH_PWRM_BASE_SIZE 0x10000 - -#define SPI_BASE_ADDRESS 0xfe010000 -#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 - -#define GPIO_BASE_SIZE 0x10000 - -#define HECI1_BASE_ADDRESS 0xfeda2000 - -#define VTD_BASE_ADDRESS 0xFED90000 -#define VTD_BASE_SIZE 0x00004000 - -/* - * I/O port address space - */ -#define SMBUS_BASE_ADDRESS 0x0efa0 -#define SMBUS_BASE_SIZE 0x20 - -#define ACPI_BASE_ADDRESS 0x1800 -#define ACPI_BASE_SIZE 0x100 - -#define TCO_BASE_ADDRESS 0x400 -#define TCO_BASE_SIZE 0x20 - -#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS -#define P2SB_SIZE (16 * MiB) - -#endif diff --git a/src/soc/intel/icelake/include/soc/irq.h b/src/soc/intel/icelake/include/soc/irq.h deleted file mode 100644 index 05d4025f25..0000000000 --- a/src/soc/intel/icelake/include/soc/irq.h +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_IRQ_H_ -#define _SOC_IRQ_H_ - -#define GPIO_IRQ14 14 -#define GPIO_IRQ15 15 - -#define PCH_IRQ10 10 -#define PCH_IRQ11 11 - -#define SCI_IRQ9 9 -#define SCI_IRQ10 10 -#define SCI_IRQ11 11 -#define SCI_IRQ20 20 -#define SCI_IRQ21 21 -#define SCI_IRQ22 22 -#define SCI_IRQ23 23 - -#define TCO_IRQ9 9 -#define TCO_IRQ10 10 -#define TCO_IRQ11 11 -#define TCO_IRQ20 20 -#define TCO_IRQ21 21 -#define TCO_IRQ22 22 -#define TCO_IRQ23 23 - -#define LPSS_I2C0_IRQ 16 -#define LPSS_I2C1_IRQ 17 -#define LPSS_I2C2_IRQ 18 -#define LPSS_I2C3_IRQ 19 -#define LPSS_I2C4_IRQ 32 -#define LPSS_I2C5_IRQ 33 -#define LPSS_SPI0_IRQ 22 -#define LPSS_SPI1_IRQ 23 -#define LPSS_SPI2_IRQ 24 -#define LPSS_UART0_IRQ 20 -#define LPSS_UART1_IRQ 21 -#define LPSS_UART2_IRQ 34 -#define SDIO_IRQ 22 - -#define cAVS_INTA_IRQ 16 -#define SMBUS_INTA_IRQ 16 -#define SMBUS_INTB_IRQ 17 -#define GbE_INTA_IRQ 16 -#define GbE_INTC_IRQ 18 -#define TRACE_HUB_INTA_IRQ 16 -#define TRACE_HUB_INTD_IRQ 19 - -#define eMMC_IRQ 16 -#define SD_IRQ 19 - -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 -#define PCIE_9_IRQ 16 -#define PCIE_10_IRQ 17 -#define PCIE_11_IRQ 18 -#define PCIE_12_IRQ 19 - -#define SATA_IRQ 16 - -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define IDER_IRQ 18 -#define KT_IRQ 19 -#define HECI_3_IRQ 16 - -#define XHCI_IRQ 16 -#define OTG_IRQ 17 -#define PMC_SRAM_IRQ 18 -#define THERMAL_IRQ 16 -#define CNViWIFI_IRQ 19 -#define UFS_IRQ 16 -#define CIO_INTA_IRQ 16 -#define CIO_INTD_IRQ 19 -#define ISH_IRQ 20 - -#define PEG_RP_INTA_IRQ 16 -#define PEG_RP_INTB_IRQ 17 -#define PEG_RP_INTC_IRQ 18 -#define PEG_RP_INTD_IRQ 19 - -#define IGFX_IRQ 16 -#define SA_THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 -#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/icelake/include/soc/itss.h b/src/soc/intel/icelake/include/soc/itss.h deleted file mode 100644 index 7051a00e9d..0000000000 --- a/src/soc/intel/icelake/include/soc/itss.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef SOC_INTEL_ICL_ITSS_H -#define SOC_INTEL_ICL_ITSS_H - -#define GPIO_IRQ_START 50 -#define GPIO_IRQ_END ITSS_MAX_IRQ - -#define ITSS_MAX_IRQ 119 -#define IRQS_PER_IPC 32 -#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) - -#endif /* SOC_INTEL_ICL_ITSS_H */ diff --git a/src/soc/intel/icelake/include/soc/me.h b/src/soc/intel/icelake/include/soc/me.h deleted file mode 100644 index 20dfcb7d71..0000000000 --- a/src/soc/intel/icelake/include/soc/me.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _ICELAKE_ME_H_ -#define _ICELAKE_ME_H_ - -/* ME Host Firmware Status register 1 */ -union me_hfsts1 { - u32 data; - struct { - u32 working_state: 4; - u32 mfg_mode: 1; - u32 fpt_bad: 1; - u32 operation_state: 3; - u32 fw_init_complete: 1; - u32 ft_bup_ld_flr: 1; - u32 update_in_progress: 1; - u32 error_code: 4; - u32 operation_mode: 4; - u32 reset_count: 4; - u32 boot_options_present: 1; - u32 reserved1: 1; - u32 bist_test_state: 1; - u32 bist_reset_request: 1; - u32 current_power_source: 2; - u32 reserved: 1; - u32 d0i3_support_valid: 1; - } __packed fields; -}; - -/* ME Host Firmware Status Register 3 */ -union me_hfsts3 { - u32 data; - struct { - u32 reserved_0: 4; - u32 fw_sku: 3; - u32 reserved_7: 2; - u32 reserved_9: 2; - u32 resered_11: 3; - u32 resered_14: 16; - u32 reserved_30: 2; - } __packed fields; -}; - -#endif /* _ICELAKE_ME_H_ */ diff --git a/src/soc/intel/icelake/include/soc/msr.h b/src/soc/intel/icelake/include/soc/msr.h deleted file mode 100644 index d716bdbcc5..0000000000 --- a/src/soc/intel/icelake/include/soc/msr.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_MSR_H_ -#define _SOC_MSR_H_ - -#include <intelblocks/msr.h> - -#define MSR_BIOS_DONE 0x151 -#define ENABLE_IA_UNTRUSTED (1 << 0) -#define MSR_VR_MISC_CONFIG2 0x636 - -#endif diff --git a/src/soc/intel/icelake/include/soc/nvs.h b/src/soc/intel/icelake/include/soc/nvs.h deleted file mode 100644 index 512945898e..0000000000 --- a/src/soc/intel/icelake/include/soc/nvs.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_NVS_H_ -#define _SOC_NVS_H_ - -#include <intelblocks/nvs.h> - -#endif diff --git a/src/soc/intel/icelake/include/soc/p2sb.h b/src/soc/intel/icelake/include/soc/p2sb.h deleted file mode 100644 index f58dfc7731..0000000000 --- a/src/soc/intel/icelake/include/soc/p2sb.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ICELAKE_P2SB_H_ -#define _SOC_ICELAKE_P2SB_H_ - -#define HPTC_OFFSET 0x60 -#define HPTC_ADDR_ENABLE_BIT (1 << 7) - -#define PCH_P2SB_EPMASK0 0x220 - -#endif diff --git a/src/soc/intel/icelake/include/soc/pch.h b/src/soc/intel/icelake/include/soc/pch.h deleted file mode 100644 index a8c3f4a447..0000000000 --- a/src/soc/intel/icelake/include/soc/pch.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ICELAKE_PCH_H_ -#define _SOC_ICELAKE_PCH_H_ - -#define PCIE_CLK_NOTUSED 0xFF -#define PCIE_CLK_LAN 0x70 -#define PCIE_CLK_FREE 0x80 - -#endif diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h deleted file mode 100644 index ce88a961a1..0000000000 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ /dev/null @@ -1,192 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ICELAKE_PCI_DEVS_H_ -#define _SOC_ICELAKE_PCI_DEVS_H_ - -#include <device/pci_def.h> - -#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) - -#if !defined(__SIMPLE_DEVICE__) -#include <device/device.h> -#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) -#else -#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) -#endif - -/* System Agent Devices */ - -#define SA_DEV_SLOT_ROOT 0x00 -#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) -#if defined(__SIMPLE_DEVICE__) -#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) -#endif - -#define SA_DEV_SLOT_IGD 0x02 -#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) -#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) - -#define SA_DEV_SLOT_DSP 0x04 -#define SA_DEVFN_DSP PCI_DEVFN(SA_DEV_SLOT_DSP, 0) -#define SA_DEV_DSP PCI_DEV(0, SA_DEV_SLOT_DSP, 0) - -/* PCH Devices */ -#define PCH_DEV_SLOT_THERMAL 0x12 -#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0) -#define PCH_DEVFN_UFS _PCH_DEVFN(THERMAL, 5) -#define PCH_DEVFN_GSPI2 _PCH_DEVFN(THERMAL, 6) -#define PCH_DEV_THERMAL _PCH_DEV(THERMAL, 0) -#define PCH_DEV_UFS _PCH_DEV(THERMAL, 5) -#define PCH_DEV_GSPI2 _PCH_DEV(THERMAL, 6) - -#define PCH_DEV_SLOT_ISH 0x13 -#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) -#define PCH_DEV_ISH _PCH_DEV(ISH, 0) - -#define PCH_DEV_SLOT_XHCI 0x14 -#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) -#define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) -#define PCH_DEVFN_CNViWIFI _PCH_DEVFN(XHCI, 3) -#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) -#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) -#define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) -#define PCH_DEV_CNViWIFI _PCH_DEV(XHCI, 3) -#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) - -#define PCH_DEV_SLOT_SIO1 0x15 -#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0) -#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO1, 1) -#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO1, 2) -#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO1, 3) -#define PCH_DEV_I2C0 _PCH_DEV(SIO1, 0) -#define PCH_DEV_I2C1 _PCH_DEV(SIO1, 1) -#define PCH_DEV_I2C2 _PCH_DEV(SIO1, 2) -#define PCH_DEV_I2C3 _PCH_DEV(SIO1, 3) - -#define PCH_DEV_SLOT_CSE 0x16 -#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) -#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) -#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2) -#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3) -#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) -#define PCH_DEVFN_CSE_4 _PCH_DEVFN(CSE, 5) -#define PCH_DEV_CSE _PCH_DEV(CSE, 0) -#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) -#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2) -#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3) -#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) -#define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5) - -#define PCH_DEV_SLOT_SATA 0x17 -#define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) -#define PCH_DEV_SATA _PCH_DEV(SATA, 0) - -#define PCH_DEV_SLOT_SIO2 0x19 -#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0) -#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1) -#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 2) -#define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0) -#define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1) -#define PCH_DEV_UART2 _PCH_DEV(SIO2, 2) - -#define PCH_DEV_SLOT_STORAGE 0x1A -#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) -#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) - -#define PCH_DEV_SLOT_PCIE 0x1c -#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) -#define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) -#define PCH_DEVFN_PCIE3 _PCH_DEVFN(PCIE, 2) -#define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE, 3) -#define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4) -#define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5) -#define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6) -#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7) -#define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0) -#define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1) -#define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2) -#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3) -#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4) -#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) -#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6) -#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7) - -#define PCH_DEV_SLOT_PCIE_1 0x1d -#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0) -#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) -#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) -#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) -#define PCH_DEVFN_PCIE13 _PCH_DEVFN(PCIE_1, 4) -#define PCH_DEVFN_PCIE14 _PCH_DEVFN(PCIE_1, 5) -#define PCH_DEVFN_PCIE15 _PCH_DEVFN(PCIE_1, 6) -#define PCH_DEVFN_PCIE16 _PCH_DEVFN(PCIE_1, 7) -#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) -#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) -#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) -#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) -#define PCH_DEV_PCIE13 _PCH_DEV(PCIE_1, 4) -#define PCH_DEV_PCIE14 _PCH_DEV(PCIE_1, 5) -#define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6) -#define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7) - -#define PCH_DEV_SLOT_PCIE_2 0x1b -#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0) -#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1) -#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2) -#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3) -#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4) -#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5) -#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6) -#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7) -#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0) -#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1) -#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2) -#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3) -#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4) -#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5) -#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6) -#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7) - -#define PCH_DEV_SLOT_SIO3 0x1e -#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0) -#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1) -#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO3, 2) -#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO3, 3) -#define PCH_DEV_UART0 _PCH_DEV(SIO3, 0) -#define PCH_DEV_UART1 _PCH_DEV(SIO3, 1) -#define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2) -#define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3) - -#define PCH_DEV_SLOT_ESPI 0x1f -#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI -#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) -#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) -#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) -#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) -#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) -#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) -#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) -#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) -#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) -#define PCH_DEV_LPC PCH_DEV_ESPI -#define PCH_DEV_P2SB _PCH_DEV(ESPI, 1) - -#if !ENV_RAMSTAGE -/* - * PCH_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets - * hidden from PCI bus after call to FSP-S. This leads to resource allocator - * dropping it from the root bus as unused device. All references to PCH_DEV_PMC - * would then return NULL and can go unnoticed if not handled properly. Since, - * this device does not have any special chip config associated with it, it is - * okay to not provide the definition for it in ramstage. - */ -#define PCH_DEV_PMC _PCH_DEV(ESPI, 2) -#endif - -#define PCH_DEV_HDA _PCH_DEV(ESPI, 3) -#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) -#define PCH_DEV_SPI _PCH_DEV(ESPI, 5) -#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) -#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7) - -#endif diff --git a/src/soc/intel/icelake/include/soc/pcr_ids.h b/src/soc/intel/icelake/include/soc/pcr_ids.h deleted file mode 100644 index c30813bc7a..0000000000 --- a/src/soc/intel/icelake/include/soc/pcr_ids.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef SOC_ICELAKE_PCR_H -#define SOC_ICELAKE_PCR_H -/* - * Port ids - */ -#define PID_EMMC 0x52 -#define PID_SDX 0x53 - -#define PID_GPIOCOM0 0x6e -#define PID_GPIOCOM1 0x6d -#define PID_GPIOCOM2 0x6c -#define PID_GPIOCOM4 0x6a -#define PID_GPIOCOM5 0x69 - -#define PID_DMI 0x88 -#define PID_PSTH 0x89 -#define PID_CSME0 0x90 -#define PID_ISCLK 0xad -#define PID_PSF1 0xba -#define PID_PSF2 0xbb -#define PID_PSF3 0xbc -#define PID_PSF4 0xbd -#define PID_SCS 0xc0 -#define PID_RTC 0xc3 -#define PID_ITSS 0xc4 -#define PID_ESPI 0xc7 -#define PID_SERIALIO 0xcb - -#endif diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h deleted file mode 100644 index 05db830b37..0000000000 --- a/src/soc/intel/icelake/include/soc/pm.h +++ /dev/null @@ -1,162 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_PM_H_ -#define _SOC_PM_H_ - -#define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) -#define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) -#define PM1_CNT 0x04 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) -#define PM1_TMR 0x08 -#define SMI_EN 0x30 -#define XHCI_SMI_EN (1 << 31) -#define ME_SMI_EN (1 << 30) -#define ESPI_SMI_EN (1 << 28) -#define GPIO_UNLOCK_SMI_EN (1 << 27) -#define INTEL_USB2_EN (1 << 18) -#define LEGACY_USB2_EN (1 << 17) -#define PERIODIC_EN (1 << 14) -#define TCO_SMI_EN (1 << 13) -#define MCSMI_EN (1 << 11) -#define BIOS_RLS (1 << 7) -#define SWSMI_TMR_EN (1 << 6) -#define APMC_EN (1 << 5) -#define SLP_SMI_EN (1 << 4) -#define LEGACY_USB_EN (1 << 3) -#define BIOS_EN (1 << 2) -#define EOS (1 << 1) -#define GBL_SMI_EN (1 << 0) -#define SMI_STS 0x34 -#define SMI_STS_BITS 32 -#define XHCI_SMI_STS_BIT 31 -#define ME_SMI_STS_BIT 30 -#define ESPI_SMI_STS_BIT 28 -#define GPIO_UNLOCK_SMI_STS_BIT 27 -#define SPI_SMI_STS_BIT 26 -#define SCC_SMI_STS_BIT 25 -#define MONITOR_STS_BIT 21 -#define PCI_EXP_SMI_STS_BIT 20 -#define SMBUS_SMI_STS_BIT 16 -#define SERIRQ_SMI_STS_BIT 15 -#define PERIODIC_STS_BIT 14 -#define TCO_STS_BIT 13 -#define DEVMON_STS_BIT 12 -#define MCSMI_STS_BIT 11 -#define GPIO_STS_BIT 10 -#define GPE0_STS_BIT 9 -#define PM1_STS_BIT 8 -#define SWSMI_TMR_STS_BIT 6 -#define APM_STS_BIT 5 -#define SMI_ON_SLP_EN_STS_BIT 4 -#define LEGACY_USB_STS_BIT 3 -#define BIOS_STS_BIT 2 -#define GPE_CNTL 0x42 -#define SWGPE_CTRL (1 << 1) -#define DEVACT_STS 0x44 -#define PM2_CNT 0x50 - -#define GPE0_REG_MAX 4 -#define GPE0_REG_SIZE 32 -#define GPE0_STS(x) (0x60 + ((x) * 4)) -#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ -#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ -#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ -#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ -#define GPE_STS_RSVD GPE_STD -#define WADT_STS (1 << 18) -#define GPIO_T2_STS (1 << 15) -#define ESPI_STS (1 << 14) -#define PME_B0_STS (1 << 13) -#define ME_SCI_STS (1 << 12) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) -#define GPE0_EN(x) (0x70 + ((x) * 4)) -#define WADT_EN (1 << 18) -#define GPIO_T2_EN (1 << 15) -#define ESPI_EN (1 << 14) -#define PME_B0_EN_BIT 13 -#define PME_B0_EN (1 << PME_B0_EN_BIT) -#define ME_SCI_EN (1 << 12) -#define PME_EN (1 << 11) -#define BATLOW_EN (1 << 10) -#define PCI_EXP_EN (1 << 9) -#define TCOSCI_EN (1 << 6) -#define SWGPE_EN (1 << 2) -#define HOT_PLUG_EN (1 << 1) - -#define EN_BLOCK 3 - -/* - * Enable SMI generation: - * - on APMC writes (io 0xb2) - * - on writes to SLP_EN (sleep states) - * - on writes to GBL_RLS (bios commands) - * - on eSPI events (does nothing on LPC systems) - * No SMIs: - * - on TCO events, unless enabled in common code - * - on microcontroller writes (io 0x62/0x66) - */ -#define ENABLE_SMI_PARAMS \ - (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) - -#define PSS_RATIO_STEP 2 -#define PSS_MAX_ENTRIES 8 -#define PSS_LATENCY_TRANSITION 10 -#define PSS_LATENCY_BUSMASTER 10 - -#if !defined(__ACPI__) - -#include <acpi/acpi.h> -#include <soc/gpe.h> -#include <soc/iomap.h> -#include <soc/smbus.h> -#include <soc/pmc.h> - -struct chipset_power_state { - uint16_t pm1_sts; - uint16_t pm1_en; - uint32_t pm1_cnt; - uint16_t tco1_sts; - uint16_t tco2_sts; - uint32_t gpe0_sts[4]; - uint32_t gpe0_en[4]; - uint32_t gen_pmcon_a; - uint32_t gen_pmcon_b; - uint32_t gblrst_cause[2]; - uint32_t prev_sleep_state; -} __packed; - -/* Get base address PMC memory mapped registers. */ -uint8_t *pmc_mmio_regs(void); - -/* Get base address of TCO I/O registers. */ -uint16_t smbus_tco_regs(void); - -/* Set the DISB after DRAM init */ -void pmc_set_disb(void); - -/* STM Support */ -uint16_t get_pmbase(void); - -#endif /* !defined(__ACPI__) */ -#endif diff --git a/src/soc/intel/icelake/include/soc/pmc.h b/src/soc/intel/icelake/include/soc/pmc.h deleted file mode 100644 index 2ca3328392..0000000000 --- a/src/soc/intel/icelake/include/soc/pmc.h +++ /dev/null @@ -1,141 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ICELAKE_PMC_H_ -#define _SOC_ICELAKE_PMC_H_ - -/* PCI Configuration Space (D31:F2): PMC */ -#define PWRMBASE 0x10 -#define ABASE 0x20 - -/* Memory mapped IO registers in PMC */ -#define GEN_PMCON_A 0x1020 -#define DC_PP_DIS (1 << 30) -#define DSX_PP_DIS (1 << 29) -#define AG3_PP_EN (1 << 28) -#define SX_PP_EN (1 << 27) -#define ALLOW_ICLK_PLL_SD_INC0 (1 << 26) -#define GBL_RST_STS (1 << 24) -#define DISB (1 << 23) -#define ALLOW_OPI_PLL_SD_INC0 (1 << 22) -#define MEM_SR (1 << 21) -#define ALLOW_SPXB_CG_INC0 (1 << 20) -#define ALLOW_L1LOW_C0 (1 << 19) -#define MS4V (1 << 18) -#define ALLOW_L1LOW_OPI_ON (1 << 17) -#define SUS_PWR_FLR (1 << 16) -#define PME_B0_S5_DIS (1 << 15) -#define PWR_FLR (1 << 14) -#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13) -#define DIS_SLP_X_STRCH_SUS_UP (1 << 12) -#define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10) -#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10) -#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10) -#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10) -#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10) -#define HOST_RST_STS (1 << 9) -#define ESPI_SMI_LOCK (1 << 8) -#define S4MAW_MASK (3 << 4) -#define S4MAW_1S (1 << 4) -#define S4MAW_2S (2 << 4) -#define S4MAW_3S (3 << 4) -#define S4MAW_4S (0 << 4) -#define S4ASE (1 << 3) -#define PER_SMI_SEL_MASK (3 << 1) -#define SMI_RATE_64S (0 << 1) -#define SMI_RATE_32S (1 << 1) -#define SMI_RATE_16S (2 << 1) -#define SMI_RATE_8S (3 << 1) -#define SLEEP_AFTER_POWER_FAIL (1 << 0) - -#define GEN_PMCON_B 0x1024 -#define SLP_STR_POL_LOCK (1 << 18) -#define ACPI_BASE_LOCK (1 << 17) -#define PM_DATA_BAR_DIS (1 << 16) -#define WOL_EN_OVRD (1 << 13) -#define BIOS_PCI_EXP_EN (1 << 10) -#define PWRBTN_LVL (1 << 9) -#define SMI_LOCK (1 << 4) -#define RTC_BATTERY_DEAD (1 << 2) - -#define ETR 0x1048 -#define CF9_LOCK (1 << 31) -#define CF9_GLB_RST (1 << 20) - -#define SSML 0x104C -#define SSML_SSL_DS (0 << 0) -#define SSML_SSL_EN (1 << 0) - -#define SSMC 0x1050 -#define SSMC_SSMS (1 << 0) - -#define SSMD 0x1054 -#define SSMD_SSD_MASK (0xffff << 0) - -#define PRSTS 0x1810 - -#define S3_PWRGATE_POL 0x1828 -#define S3DC_GATE_SUS (1 << 1) -#define S3AC_GATE_SUS (1 << 0) - -#define S4_PWRGATE_POL 0x182c -#define S4DC_GATE_SUS (1 << 1) -#define S4AC_GATE_SUS (1 << 0) - -#define S5_PWRGATE_POL 0x1830 -#define S5DC_GATE_SUS (1 << 15) -#define S5AC_GATE_SUS (1 << 14) - -#define DSX_CFG 0x1834 -#define REQ_CNV_NOWAKE_DSX (1 << 4) -#define REQ_BATLOW_DSX (1 << 3) -#define DSX_EN_WAKE_PIN (1 << 2) -#define DSX_DIS_AC_PRESENT_PD (1 << 1) -#define DSX_EN_LAN_WAKE_PIN (1 << 0) -#define DSX_CFG_MASK (0x1f << 0) - -#define PMSYNC_TPR_CFG 0x18C4 -#define PCH2CPU_TPR_CFG_LOCK (1 << 31) -#define PCH2CPU_TT_EN (1 << 26) - -#define PCH_PWRM_ACPI_TMR_CTL 0x18FC -#define ACPI_TIM_DIS (1 << 1) -#define GPIO_GPE_CFG 0x1920 -#define GPE0_DWX_MASK 0xf -#define GPE0_DW_SHIFT(x) (4*(x)) - -#define PMC_GPP_G 0x0 -#define PMC_GPP_B 0x1 -#define PMC_GPP_A 0x2 -#define PMC_GPP_R 0x3 -#define PMC_GPP_S 0x4 -#define PMC_GPD 0x5 -#define PMC_GPP_H 0x6 -#define PMC_GPP_D 0x7 -#define PMC_GPP_F 0x8 -#define PMC_GPP_C 0xA -#define PMC_GPP_E 0xB - -#define GBLRST_CAUSE0 0x1924 -#define GBLRST_CAUSE0_THERMTRIP (1 << 5) -#define GBLRST_CAUSE1 0x1928 - -#define SLP_S0_RES 0x193c - -#define CPPMVRIC 0x1B1C -#define XTALSDQDIS (1 << 22) - -#define IRQ_REG ACTL -#define SCI_IRQ_ADJUST 0 -#define ACTL 0x1BD8 -#define PWRM_EN (1 << 8) -#define ACPI_EN (1 << 7) -#define SCI_IRQ_SEL (7 << 0) - -#define SCIS_IRQ9 0 -#define SCIS_IRQ10 1 -#define SCIS_IRQ11 2 -#define SCIS_IRQ20 4 -#define SCIS_IRQ21 5 -#define SCIS_IRQ22 6 -#define SCIS_IRQ23 7 -#endif diff --git a/src/soc/intel/icelake/include/soc/ramstage.h b/src/soc/intel/icelake/include/soc/ramstage.h deleted file mode 100644 index 8188fbdb84..0000000000 --- a/src/soc/intel/icelake/include/soc/ramstage.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_RAMSTAGE_H_ -#define _SOC_RAMSTAGE_H_ - -#include <device/device.h> -#include <fsp/api.h> -#include <fsp/util.h> -#include <soc/soc_chip.h> - -void mainboard_silicon_init_params(FSP_S_CONFIG *params); -void soc_init_pre_device(void *chip_info); - -#endif diff --git a/src/soc/intel/icelake/include/soc/romstage.h b/src/soc/intel/icelake/include/soc/romstage.h deleted file mode 100644 index ba44f2df26..0000000000 --- a/src/soc/intel/icelake/include/soc/romstage.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ROMSTAGE_H_ -#define _SOC_ROMSTAGE_H_ - -#include <fsp/api.h> - -void mainboard_memory_init_params(FSPM_UPD *mupd); -void systemagent_early_init(void); - -/* Board type */ -enum board_type { - BOARD_TYPE_MOBILE = 0, - BOARD_TYPE_DESKTOP = 1, - BOARD_TYPE_ULT_ULX = 5, - BOARD_TYPE_SERVER = 7 -}; - -#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/icelake/include/soc/serialio.h b/src/soc/intel/icelake/include/soc/serialio.h deleted file mode 100644 index c186109e11..0000000000 --- a/src/soc/intel/icelake/include/soc/serialio.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SERIALIO_H_ -#define _SERIALIO_H_ - -enum { - PchSerialIoDisabled, - PchSerialIoPci, - PchSerialIoHidden, - PchSerialIoLegacyUart, - PchSerialIoSkipInit -}; - -enum { - PchSerialIoIndexI2C0, - PchSerialIoIndexI2C1, - PchSerialIoIndexI2C2, - PchSerialIoIndexI2C3, - PchSerialIoIndexI2C4, - PchSerialIoIndexI2C5 -}; - -enum { - PchSerialIoIndexGSPI0, - PchSerialIoIndexGSPI1, - PchSerialIoIndexGSPI2 -}; - -enum { - PchSerialIoIndexUART0, - PchSerialIoIndexUART1, - PchSerialIoIndexUART2 -}; - -#endif diff --git a/src/soc/intel/icelake/include/soc/smbus.h b/src/soc/intel/icelake/include/soc/smbus.h deleted file mode 100644 index c865fbe94e..0000000000 --- a/src/soc/intel/icelake/include/soc/smbus.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_SMBUS_H_ -#define _SOC_SMBUS_H_ - -#include <intelpch/smbus.h> - -#endif diff --git a/src/soc/intel/icelake/include/soc/soc_chip.h b/src/soc/intel/icelake/include/soc/soc_chip.h deleted file mode 100644 index 0a58db3ab0..0000000000 --- a/src/soc/intel/icelake/include/soc/soc_chip.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ICELAKE_SOC_CHIP_H_ -#define _SOC_ICELAKE_SOC_CHIP_H_ - -#include "../../chip.h" - -#endif /* _SOC_ICELAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/icelake/include/soc/systemagent.h b/src/soc/intel/icelake/include/soc/systemagent.h deleted file mode 100644 index ef648a66b3..0000000000 --- a/src/soc/intel/icelake/include/soc/systemagent.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef SOC_ICELAKE_SYSTEMAGENT_H -#define SOC_ICELAKE_SYSTEMAGENT_H - -#include <intelblocks/systemagent.h> - -/* Device 0:0.0 PCI configuration space */ - -#define EPBAR 0x40 -#define DMIBAR 0x68 -#define CAPID0_A 0xe4 - -#define BIOS_RESET_CPL 0x5da8 -#define EDRAMBAR 0x5408 -#define REGBAR 0x5420 - -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 - -#define IMRBASE 0x6A40 -#define IMRLIMIT 0x6A48 - -#endif diff --git a/src/soc/intel/icelake/include/soc/usb.h b/src/soc/intel/icelake/include/soc/usb.h deleted file mode 100644 index 69d2d31a4c..0000000000 --- a/src/soc/intel/icelake/include/soc/usb.h +++ /dev/null @@ -1,138 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_USB_H_ -#define _SOC_USB_H_ - -#include <stdint.h> - -/* Per Port HS Transmitter Emphasis */ -#define USB2_EMP_OFF 0 -#define USB2_DE_EMP_ON 1 -#define USB2_PRE_EMP_ON 2 -#define USB2_DE_EMP_ON_PRE_EMP_ON 3 - -/* Per Port Half Bit Pre-emphasis */ -#define USB2_FULL_BIT_PRE_EMP 0 -#define USB2_HALF_BIT_PRE_EMP 1 - -/* Per Port HS Preemphasis Bias */ -#define USB2_BIAS_0MV 0 -#define USB2_BIAS_11P25MV 1 -#define USB2_BIAS_16P9MV 2 -#define USB2_BIAS_28P15MV 3 -#define USB2_BIAS_39P35MV 5 -#define USB2_BIAS_45MV 6 -#define USB2_BIAS_56P3MV 7 - -struct usb2_port_config { - uint8_t enable; - uint8_t ocpin; - uint8_t tx_bias; - uint8_t tx_emp_enable; - uint8_t pre_emp_bias; - uint8_t pre_emp_bit; -}; - -/* USB Overcurrent pins definition */ -enum { - OC0 = 0, - OC1, - OC2, - OC3, - OC4, - OC5, - OC6, - OC7, - OCMAX, - OC_SKIP = 0xff, /* Skip OC programming */ -}; - -/* Standard USB Port based on length: - * - External - * - Back Panel - * - OTG - * - M.2 - * - Internal device down */ - -#define USB2_PORT_EMPTY { \ - .enable = 0, \ - .ocpin = OC_SKIP, \ - .tx_bias = USB2_BIAS_0MV, \ - .tx_emp_enable = USB2_EMP_OFF, \ - .pre_emp_bias = USB2_BIAS_0MV, \ - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ -} - -/* Length = 11.5"-12" */ -#define USB2_PORT_LONG(pin) { \ - .enable = 1, \ - .ocpin = (pin), \ - .tx_bias = USB2_BIAS_39P35MV, \ - .tx_emp_enable = USB2_PRE_EMP_ON, \ - .pre_emp_bias = USB2_BIAS_56P3MV, \ - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ -} - -/* Length = 6"-11.49" */ -#define USB2_PORT_MID(pin) { \ - .enable = 1, \ - .ocpin = (pin), \ - .tx_bias = USB2_BIAS_0MV, \ - .tx_emp_enable = USB2_PRE_EMP_ON, \ - .pre_emp_bias = USB2_BIAS_56P3MV, \ - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ -} - -/* Length = 3"-5.99" */ -#define USB2_PORT_SHORT(pin) { \ - .enable = 1, \ - .ocpin = (pin), \ - .tx_bias = USB2_BIAS_39P35MV, \ - .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \ - .pre_emp_bias = USB2_BIAS_39P35MV, \ - .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ -} - -/* Max TX and Pre-emp settings */ -#define USB2_PORT_MAX(pin) { \ - .enable = 1, \ - .ocpin = (pin), \ - .tx_bias = USB2_BIAS_56P3MV, \ - .tx_emp_enable = USB2_PRE_EMP_ON, \ - .pre_emp_bias = USB2_BIAS_56P3MV, \ - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ -} - -/* Type-C Port, no BC1.2 charge detect module / MUX - * Length = 3.0" - 9.00" */ -#define USB2_PORT_TYPE_C(pin) { \ - .enable = 1, \ - .ocpin = (pin), \ - .tx_bias = USB2_BIAS_0MV, \ - .tx_emp_enable = USB2_PRE_EMP_ON, \ - .pre_emp_bias = USB2_BIAS_56P3MV, \ - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ -} - -struct usb3_port_config { - uint8_t enable; - uint8_t ocpin; - uint8_t tx_de_emp; - uint8_t tx_downscale_amp; -}; - -#define USB3_PORT_EMPTY { \ - .enable = 0, \ - .ocpin = OC_SKIP, \ - .tx_de_emp = 0x00, \ - .tx_downscale_amp = 0x00, \ -} - -#define USB3_PORT_DEFAULT(pin) { \ - .enable = 1, \ - .ocpin = (pin), \ - .tx_de_emp = 0x0, \ - .tx_downscale_amp = 0x00, \ -} - -#endif diff --git a/src/soc/intel/icelake/lockdown.c b/src/soc/intel/icelake/lockdown.c deleted file mode 100644 index 3205c7f303..0000000000 --- a/src/soc/intel/icelake/lockdown.c +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/mmio.h> -#include <intelblocks/cfg.h> -#include <intelblocks/pmclib.h> -#include <intelpch/lockdown.h> -#include <soc/pm.h> - -static void pmc_lock_pmsync(void) -{ - uint8_t *pmcbase; - uint32_t pmsyncreg; - - pmcbase = pmc_mmio_regs(); - - pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); - pmsyncreg |= PCH2CPU_TPR_CFG_LOCK; - write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); -} - -static void pmc_lock_abase(void) -{ - uint8_t *pmcbase; - uint32_t reg32; - - pmcbase = pmc_mmio_regs(); - - reg32 = read32(pmcbase + GEN_PMCON_B); - reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); - write32(pmcbase + GEN_PMCON_B, reg32); -} - -static void pmc_lock_smi(void) -{ - uint8_t *pmcbase; - uint8_t reg8; - - pmcbase = pmc_mmio_regs(); - - reg8 = read8(pmcbase + GEN_PMCON_B); - reg8 |= SMI_LOCK; - write8(pmcbase + GEN_PMCON_B, reg8); -} - -static void pmc_lockdown_cfg(int chipset_lockdown) -{ - /* PMSYNC */ - pmc_lock_pmsync(); - /* Lock down ABASE and sleep stretching policy */ - pmc_lock_abase(); - /* Make sure payload/OS can't trigger global reset */ - pmc_global_reset_disable_and_lock(); - - if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) - pmc_lock_smi(); -} - -void soc_lockdown_config(int chipset_lockdown) -{ - /* PMC lock down configuration */ - pmc_lockdown_cfg(chipset_lockdown); -} diff --git a/src/soc/intel/icelake/me.c b/src/soc/intel/icelake/me.c deleted file mode 100644 index c494fa5c0b..0000000000 --- a/src/soc/intel/icelake/me.c +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootstate.h> -#include <intelblocks/cse.h> -#include <console/console.h> -#include <soc/me.h> -#include <stdint.h> - -/* Host Firmware Status Register 2 */ -union me_hfsts2 { - uint32_t data; - struct { - uint32_t nftp_load_failure : 1; - uint32_t icc_prog_status : 2; - uint32_t invoke_mebx : 1; - uint32_t cpu_replaced : 1; - uint32_t rsvd0 : 1; - uint32_t mfs_failure : 1; - uint32_t warm_reset_rqst : 1; - uint32_t cpu_replaced_valid : 1; - uint32_t low_power_state : 1; - uint32_t me_power_gate : 1; - uint32_t ipu_needed : 1; - uint32_t forced_safe_boot : 1; - uint32_t rsvd1 : 2; - uint32_t listener_change : 1; - uint32_t status_data : 8; - uint32_t current_pmevent : 4; - uint32_t phase : 4; - } __packed fields; -}; - -/* Host Firmware Status Register 4 */ -union me_hfsts4 { - uint32_t data; - struct { - uint32_t rsvd0 : 9; - uint32_t enforcement_flow : 1; - uint32_t sx_resume_type : 1; - uint32_t rsvd1 : 1; - uint32_t tpms_disconnected : 1; - uint32_t rvsd2 : 1; - uint32_t fwsts_valid : 1; - uint32_t boot_guard_self_test : 1; - uint32_t rsvd3 : 16; - } __packed fields; -}; - -/* Host Firmware Status Register 5 */ -union me_hfsts5 { - uint32_t data; - struct { - uint32_t acm_active : 1; - uint32_t valid : 1; - uint32_t result_code_source : 1; - uint32_t error_status_code : 5; - uint32_t acm_done_sts : 1; - uint32_t timeout_count : 7; - uint32_t scrtm_indicator : 1; - uint32_t inc_boot_guard_acm : 4; - uint32_t inc_key_manifest : 4; - uint32_t inc_boot_policy : 4; - uint32_t rsvd0 : 2; - uint32_t start_enforcement : 1; - } __packed fields; -}; - -/* Host Firmware Status Register 6 */ -union me_hfsts6 { - uint32_t data; - struct { - uint32_t force_boot_guard_acm : 1; - uint32_t cpu_debug_disable : 1; - uint32_t bsp_init_disable : 1; - uint32_t protect_bios_env : 1; - uint32_t rsvd0 : 2; - uint32_t error_enforce_policy : 2; - uint32_t measured_boot : 1; - uint32_t verified_boot : 1; - uint32_t boot_guard_acmsvn : 4; - uint32_t kmsvn : 4; - uint32_t bpmsvn : 4; - uint32_t key_manifest_id : 4; - uint32_t boot_policy_status : 1; - uint32_t error : 1; - uint32_t boot_guard_disable : 1; - uint32_t fpf_disable : 1; - uint32_t fpf_soc_lock : 1; - uint32_t txt_support : 1; - } __packed fields; -}; - -static void dump_me_status(void *unused) -{ - union me_hfsts1 hfsts1; - union me_hfsts2 hfsts2; - union me_hfsts3 hfsts3; - union me_hfsts4 hfsts4; - union me_hfsts5 hfsts5; - union me_hfsts6 hfsts6; - - if (!is_cse_enabled()) - return; - - hfsts1.data = me_read_config32(PCI_ME_HFSTS1); - hfsts2.data = me_read_config32(PCI_ME_HFSTS2); - hfsts3.data = me_read_config32(PCI_ME_HFSTS3); - hfsts4.data = me_read_config32(PCI_ME_HFSTS4); - hfsts5.data = me_read_config32(PCI_ME_HFSTS5); - hfsts6.data = me_read_config32(PCI_ME_HFSTS6); - - printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", hfsts1.data); - printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.data); - printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", hfsts3.data); - printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", hfsts4.data); - printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); - printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); - - printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfsts1.fields.mfg_mode ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", - hfsts1.fields.fpt_bad ? "BAD" : "OK"); - printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", - hfsts1.fields.ft_bup_ld_flr ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", - hfsts1.fields.fw_init_complete ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", - hfsts1.fields.boot_options_present ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", - hfsts1.fields.update_in_progress ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", - hfsts1.fields.d0i3_support_valid ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", - hfsts2.fields.low_power_state ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", - hfsts2.fields.cpu_replaced ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", - hfsts2.fields.cpu_replaced_valid ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Current Working State : %u\n", - hfsts1.fields.working_state); - printk(BIOS_DEBUG, "ME: Current Operation State : %u\n", - hfsts1.fields.operation_state); - printk(BIOS_DEBUG, "ME: Current Operation Mode : %u\n", - hfsts1.fields.operation_mode); - printk(BIOS_DEBUG, "ME: Error Code : %u\n", - hfsts1.fields.error_code); - printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", - hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: TXT Support : %s\n", - hfsts6.fields.txt_support ? "YES" : "NO"); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); diff --git a/src/soc/intel/icelake/p2sb.c b/src/soc/intel/icelake/p2sb.c deleted file mode 100644 index 169cde6147..0000000000 --- a/src/soc/intel/icelake/p2sb.c +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <intelblocks/p2sb.h> - -void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) -{ - uint32_t mask; - - if (count != P2SB_EP_MASK_MAX_REG) { - printk(BIOS_ERR, "Unable to program EPMASK registers\n"); - return; - } - - /* Remove the host accessing right to PSF register range. - * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband - * access for PCI Root Bridge. - */ - mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); - - ep_mask[P2SB_EP_MASK_5_REG] = mask; - - /* - * Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband - * access for Broadcast and Multicast. - */ - mask = (1 << 31) | (1 << 30); - - ep_mask[P2SB_EP_MASK_7_REG] = mask; -} diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c deleted file mode 100644 index c0096007be..0000000000 --- a/src/soc/intel/icelake/pmc.c +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootstate.h> -#include <console/console.h> -#include <device/mmio.h> -#include <device/device.h> -#include <intelblocks/pmc.h> -#include <intelblocks/pmclib.h> -#include <intelblocks/rtc.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/soc_chip.h> - -static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) -{ - uint32_t reg; - uint8_t *pmcbase = pmc_mmio_regs(); - - printk(BIOS_DEBUG, "%sabling Deep S%c\n", - enable ? "En" : "Dis", sx + '0'); - reg = read32(pmcbase + offset); - if (enable) - reg |= mask; - else - reg &= ~mask; - write32(pmcbase + offset, reg); -} - -static void config_deep_s5(int on_ac, int on_dc) -{ - /* Treat S4 the same as S5. */ - config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); - config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); - config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); - config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); -} - -static void config_deep_s3(int on_ac, int on_dc) -{ - config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); - config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); -} - -static void config_deep_sx(uint32_t deepsx_config) -{ - uint32_t reg; - uint8_t *pmcbase = pmc_mmio_regs(); - - reg = read32(pmcbase + DSX_CFG); - reg &= ~DSX_CFG_MASK; - reg |= deepsx_config; - write32(pmcbase + DSX_CFG, reg); -} - -static void pmc_init(void *unused) -{ - const config_t *config = config_of_soc(); - - rtc_init(); - - pmc_set_power_failure_state(true); - pmc_gpe_init(); - - pmc_set_acpi_mode(); - - config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); - config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); - config_deep_sx(config->deep_sx_config); - - /* - * Disable ACPI PM timer based on Kconfig - * - * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. - * Disabling ACPI PM timer also switches off TCO - */ - if (!CONFIG(USE_PM_ACPI_TIMER)) - setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); - - /* - * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits) - * - * Perform the PMCON status bit clear operation from `.final` - * to cover any such chances where later boot stage requested a global - * reset and PMCON status bit remains set. - */ - pmc_clear_pmcon_sts(); -} - -/* -* Initialize PMC controller. -* -* PMC controller gets hidden from PCI bus during FSP-Silicon init call. -* Hence PCI enumeration can't be used to initialize bus device and -* allocate resources. -*/ -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL); diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c deleted file mode 100644 index 9f7b72c718..0000000000 --- a/src/soc/intel/icelake/pmutil.c +++ /dev/null @@ -1,280 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Helper functions for dealing with power management registers - * and the differences between PCH variants. - */ - -#define __SIMPLE_DEVICE__ - -#include <acpi/acpi_pm.h> -#include <device/mmio.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_def.h> -#include <console/console.h> -#include <intelblocks/pmclib.h> -#include <intelblocks/rtc.h> -#include <intelblocks/tco.h> -#include <soc/espi.h> -#include <soc/gpe.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/smbus.h> -#include <soc/soc_chip.h> -#include <security/vboot/vbnv.h> - -/* - * SMI - */ - -const char *const *soc_smi_sts_array(size_t *a) -{ - static const char *const smi_sts_bits[] = { - [BIOS_STS_BIT] = "BIOS", - [LEGACY_USB_STS_BIT] = "LEGACY_USB", - [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", - [APM_STS_BIT] = "APM", - [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", - [PM1_STS_BIT] = "PM1", - [GPE0_STS_BIT] = "GPE0", - [GPIO_STS_BIT] = "GPI", - [MCSMI_STS_BIT] = "MCSMI", - [DEVMON_STS_BIT] = "DEVMON", - [TCO_STS_BIT] = "TCO", - [PERIODIC_STS_BIT] = "PERIODIC", - [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI", - [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", - [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", - [MONITOR_STS_BIT] = "MONITOR", - [SPI_SMI_STS_BIT] = "SPI", - [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK", - [ESPI_SMI_STS_BIT] = "ESPI_SMI", - }; - - *a = ARRAY_SIZE(smi_sts_bits); - return smi_sts_bits; -} - -/* - * TCO - */ - -const char *const *soc_tco_sts_array(size_t *a) -{ - static const char *const tco_sts_bits[] = { - [0] = "NMI2SMI", - [1] = "SW_TCO", - [2] = "TCO_INT", - [3] = "TIMEOUT", - [7] = "NEWCENTURY", - [8] = "BIOSWR", - [9] = "DMISCI", - [10] = "DMISMI", - [12] = "DMISERR", - [13] = "SLVSEL", - [16] = "INTRD_DET", - [17] = "SECOND_TO", - [18] = "BOOT", - [20] = "SMLINK_SLV" - }; - - *a = ARRAY_SIZE(tco_sts_bits); - return tco_sts_bits; -} - -/* - * GPE0 - */ - -const char *const *soc_std_gpe_sts_array(size_t *a) -{ - static const char *const gpe_sts_bits[] = { - [1] = "HOTPLUG", - [2] = "SWGPE", - [6] = "TCO_SCI", - [7] = "SMB_WAK", - [9] = "PCI_EXP", - [10] = "BATLOW", - [11] = "PME", - [12] = "ME", - [13] = "PME_B0", - [14] = "eSPI", - [15] = "GPIO Tier-2", - [16] = "LAN_WAKE", - [18] = "WADT" - }; - - *a = ARRAY_SIZE(gpe_sts_bits); - return gpe_sts_bits; -} - -void pmc_set_disb(void) -{ - /* Set the DISB after DRAM init */ - uint8_t disb_val; - /* Only care about bits [23:16] of register GEN_PMCON_A */ - uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2); - - disb_val = read8(addr); - disb_val |= (DISB >> 16); - - /* Don't clear bits that are write-1-to-clear */ - disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16); - write8(addr, disb_val); -} - -/* - * PMC controller gets hidden from PCI bus - * during FSP-Silicon init call. Hence PWRMBASE - * can't be accessible using PCI configuration space - * read/write. - */ -uint8_t *pmc_mmio_regs(void) -{ - return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; -} - -uintptr_t soc_read_pmc_base(void) -{ - return (uintptr_t)pmc_mmio_regs(); -} - -uint32_t *soc_pmc_etr_addr(void) -{ - return (uint32_t *)(soc_read_pmc_base() + ETR); -} - -void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) -{ - DEVTREE_CONST struct soc_intel_icelake_config *config; - - config = config_of_soc(); - - /* Assign to out variable */ - *dw0 = config->gpe0_dw0; - *dw1 = config->gpe0_dw1; - *dw2 = config->gpe0_dw2; -} - -static int rtc_failed(uint32_t gen_pmcon_b) -{ - return !!(gen_pmcon_b & RTC_BATTERY_DEAD); -} - -static void clear_rtc_failed(void) -{ - clrbits8(pmc_mmio_regs() + GEN_PMCON_B, RTC_BATTERY_DEAD); -} - -static int check_rtc_failed(uint32_t gen_pmcon_b) -{ - const int failed = rtc_failed(gen_pmcon_b); - if (failed) { - clear_rtc_failed(); - printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", failed); - } - - return failed; -} - -int soc_get_rtc_failed(void) -{ - const struct chipset_power_state *ps; - - if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0) - return 1; - - return check_rtc_failed(ps->gen_pmcon_b); -} - -int vbnv_cmos_failed(void) -{ - return check_rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); -} - -static inline int deep_s3_enabled(void) -{ - uint32_t deep_s3_pol; - - deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); - return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); -} - -/* Return 0, 3, or 5 to indicate the previous sleep state. */ -int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) -{ - /* - * Check for any power failure to determine if this a wake from - * S5 because the PCH does not set the WAK_STS bit when waking - * from a true G3 state. - */ - if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))) - prev_sleep_state = ACPI_S5; - - /* - * If waking from S3 determine if deep S3 is enabled. If not, - * need to check both deep sleep well and normal suspend well. - * Otherwise just check deep sleep well. - */ - if (prev_sleep_state == ACPI_S3) { - /* PWR_FLR represents deep sleep power well loss. */ - uint32_t mask = PWR_FLR; - - /* If deep s3 isn't enabled check the suspend well too. */ - if (!deep_s3_enabled()) - mask |= SUS_PWR_FLR; - - if (ps->gen_pmcon_a & mask) - prev_sleep_state = ACPI_S5; - } - - return prev_sleep_state; -} - -void soc_fill_power_state(struct chipset_power_state *ps) -{ - uint8_t *pmc; - - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); - - printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); - - pmc = pmc_mmio_regs(); - ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); - ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); - ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); - ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); - - printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", - ps->gen_pmcon_a, ps->gen_pmcon_b); - - printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", - ps->gblrst_cause[0], ps->gblrst_cause[1]); -} - -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t)ACPI_BASE_ADDRESS; -} - -/* - * Set which power state system will be after reapplying - * the power (from G3 State) - */ -void pmc_soc_set_afterg3_en(const bool on) -{ - uint8_t reg8; - uint8_t *const pmcbase = pmc_mmio_regs(); - - reg8 = read8(pmcbase + GEN_PMCON_A); - if (on) - reg8 &= ~SLEEP_AFTER_POWER_FAIL; - else - reg8 |= SLEEP_AFTER_POWER_FAIL; - write8(pmcbase + GEN_PMCON_A, reg8); -} diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c deleted file mode 100644 index bc5815ac7a..0000000000 --- a/src/soc/intel/icelake/reset.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <soc/intel/common/reset.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset()) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} diff --git a/src/soc/intel/icelake/romstage/Makefile.inc b/src/soc/intel/icelake/romstage/Makefile.inc deleted file mode 100644 index 99c1d2ca25..0000000000 --- a/src/soc/intel/icelake/romstage/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -romstage-y += fsp_params.c -romstage-y += ../../../../cpu/intel/car/romstage.c -romstage-y += romstage.c -romstage-y += systemagent.c diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c deleted file mode 100644 index 7ddf6257ac..0000000000 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <assert.h> -#include <console/console.h> -#include <fsp/util.h> -#include <intelblocks/cpulib.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> -#include <soc/soc_chip.h> - -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, - const struct soc_intel_icelake_config *config) -{ - unsigned int i; - uint32_t mask = 0; - - /* - * If IGD is enabled, set IGD stolen size to 60MB. - * Otherwise, skip IGD init in FSP. - */ - m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD); - m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0; - - m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->SaGv = config->SaGv; - m_cfg->UserBd = BOARD_TYPE_ULT_ULX; - m_cfg->RMT = config->RMT; - m_cfg->SkipMbpHob = 1; - - /* If Audio Codec is enabled, enable FSP UPD */ - m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA); - - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1 << i); - } - m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = get_valid_prmrr_size(); - m_cfg->EnableC6Dram = config->enable_c6dram; - /* Disable BIOS Guard */ - m_cfg->BiosGuard = 0; - /* Disable Cpu Ratio Override temporary. */ - m_cfg->CpuRatio = 0; - m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; - m_cfg->PcdDebugInterfaceFlags = - CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; - - /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ - m_cfg->VmxEnable = CONFIG(ENABLE_VMX); -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const struct soc_intel_icelake_config *config; - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - - config = config_of_soc(); - - soc_memory_init_params(m_cfg, config); - - /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; - /* Set debug probe type */ - m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ICELAKE_DEBUG_CONSENT; - - /* Vt-D config */ - m_cfg->VtdDisable = 0; - - mainboard_memory_init_params(mupd); -} - -__weak void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -} diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c deleted file mode 100644 index 366ba3fa3a..0000000000 --- a/src/soc/intel/icelake/romstage/romstage.c +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/romstage.h> -#include <cbmem.h> -#include <console/console.h> -#include <fsp/util.h> -#include <intelblocks/cfg.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <intelblocks/smbus.h> -#include <memory_info.h> -#include <soc/intel/common/smbios.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/romstage.h> -#include <soc/soc_chip.h> -#include <string.h> - -#define FSP_SMBIOS_MEMORY_INFO_GUID \ -{ \ - 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ - 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ -} - -/* Memory Channel Present Status */ -enum { - CHANNEL_NOT_PRESENT, - CHANNEL_DISABLED, - CHANNEL_PRESENT -}; - -/* Save the DIMM information for SMBIOS table 17 */ -static void save_dimm_info(void) -{ - int channel, dimm, dimm_max, index; - size_t hob_size; - const CONTROLLER_INFO *ctrlr_info; - const CHANNEL_INFO *channel_info; - const DIMM_INFO *src_dimm; - struct dimm_info *dest_dimm; - struct memory_info *mem_info; - const MEMORY_INFO_DATA_HOB *memory_info_hob; - const uint8_t smbios_memory_info_guid[16] = - FSP_SMBIOS_MEMORY_INFO_GUID; - - /* Locate the memory info HOB, presence validated by raminit */ - memory_info_hob = fsp_find_extension_hob_by_guid( - smbios_memory_info_guid, - &hob_size); - if (memory_info_hob == NULL || hob_size == 0) { - printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); - return; - } - - /* - * Allocate CBMEM area for DIMM information used to populate SMBIOS - * table 17 - */ - mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - if (mem_info == NULL) { - printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); - return; - } - memset(mem_info, 0, sizeof(*mem_info)); - - /* Describe the first N DIMMs in the system */ - index = 0; - dimm_max = ARRAY_SIZE(mem_info->dimm); - ctrlr_info = &memory_info_hob->Controller[0]; - for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { - channel_info = &ctrlr_info->ChannelInfo[channel]; - if (channel_info->Status != CHANNEL_PRESENT) - continue; - for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { - src_dimm = &channel_info->DimmInfo[dimm]; - dest_dimm = &mem_info->dimm[index]; - - if (src_dimm->Status != DIMM_PRESENT) - continue; - - u8 memProfNum = memory_info_hob->MemoryProfile; - - /* Populate the DIMM information */ - dimm_info_fill(dest_dimm, - src_dimm->DimmCapacity, - memory_info_hob->MemoryType, - memory_info_hob->ConfiguredMemoryClockSpeed, - src_dimm->RankInDimm, - channel_info->ChannelId, - src_dimm->DimmId, - (const char *)src_dimm->ModulePartNum, - sizeof(src_dimm->ModulePartNum), - src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth, - memory_info_hob->VddVoltage[memProfNum], - memory_info_hob->EccSupport, - src_dimm->MfgId, - src_dimm->SpdModuleType, - 0); - index++; - } - } - mem_info->dimm_cnt = index; - printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); -} - -void mainboard_romstage_entry(void) -{ - bool s3wake; - struct chipset_power_state *ps = pmc_get_power_state(); - - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ - systemagent_early_init(); - /* Program SMBus base address and enable it */ - smbus_common_init(); - /* initialize Heci interface */ - cse_init(HECI1_BASE_ADDRESS); - - s3wake = pmc_fill_power_state(ps) == ACPI_S3; - fsp_memory_init(s3wake); - pmc_set_disb(); - if (!s3wake) - save_dimm_info(); -} diff --git a/src/soc/intel/icelake/romstage/systemagent.c b/src/soc/intel/icelake/romstage/systemagent.c deleted file mode 100644 index 8502e29843..0000000000 --- a/src/soc/intel/icelake/romstage/systemagent.c +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <intelblocks/systemagent.h> -#include <soc/iomap.h> -#include <soc/romstage.h> -#include <soc/systemagent.h> - -void systemagent_early_init(void) -{ - static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { - { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, - { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, - { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, - }; - - static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { - { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, - { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, - }; - - /* Set Fixed MMIO address into PCI configuration space */ - sa_set_pci_bar(soc_fixed_pci_resources, - ARRAY_SIZE(soc_fixed_pci_resources)); - /* Set Fixed MMIO address into MCH base address */ - sa_set_mch_bar(soc_fixed_mch_resources, - ARRAY_SIZE(soc_fixed_mch_resources)); - /* Enable PAM registers */ - enable_pam_region(); -} diff --git a/src/soc/intel/icelake/sd.c b/src/soc/intel/icelake/sd.c deleted file mode 100644 index a4b89c5803..0000000000 --- a/src/soc/intel/icelake/sd.c +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/sd.h> -#include <soc/soc_chip.h> - -int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, const struct device *dev) -{ - config_t *config = config_of(dev); - - if (!config->sdcard_cd_gpio) - return -1; - - gpio->type = ACPI_GPIO_TYPE_INTERRUPT; - gpio->pull = ACPI_GPIO_PULL_NONE; - gpio->irq.mode = ACPI_IRQ_EDGE_TRIGGERED; - gpio->irq.polarity = ACPI_IRQ_ACTIVE_BOTH; - gpio->irq.shared = ACPI_IRQ_SHARED; - gpio->irq.wake = ACPI_IRQ_WAKE; - gpio->interrupt_debounce_timeout = 10000; /* 100ms */ - gpio->pin_count = 1; - gpio->pins[0] = config->sdcard_cd_gpio; - - return 0; -} diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c deleted file mode 100644 index 7958da6bb6..0000000000 --- a/src/soc/intel/icelake/smihandler.c +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/pci_def.h> -#include <intelblocks/cse.h> -#include <intelblocks/smihandler.h> -#include <soc/soc_chip.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> - -/* - * Specific SOC SMI handler during ramstage finalize phase - * - * BIOS can't make CSME function disable as is due to POSTBOOT_SAI - * restriction in place from ICP chipset. Hence create SMI Handler to - * perform CSME function disabling logic during SMM mode. - */ -void smihandler_soc_at_finalize(void) -{ - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) - heci1_disable(); -} - -const smi_handler_t southbridge_smi[SMI_STS_BITS] = { - [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, - [APM_STS_BIT] = smihandler_southbridge_apmc, - [PM1_STS_BIT] = smihandler_southbridge_pm1, - [GPE0_STS_BIT] = smihandler_southbridge_gpe0, - [GPIO_STS_BIT] = smihandler_southbridge_gpi, - [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, - [MCSMI_STS_BIT] = smihandler_southbridge_mc, -#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) - [TCO_STS_BIT] = smihandler_southbridge_tco, -#endif - [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, - [MONITOR_STS_BIT] = smihandler_southbridge_monitor, -}; diff --git a/src/soc/intel/icelake/spi.c b/src/soc/intel/icelake/spi.c deleted file mode 100644 index 8a7ed73b47..0000000000 --- a/src/soc/intel/icelake/spi.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <intelblocks/spi.h> -#include <soc/pci_devs.h> - -int spi_soc_devfn_to_bus(unsigned int devfn) -{ - switch (devfn) { - case PCH_DEVFN_GSPI0: - return 1; - case PCH_DEVFN_GSPI1: - return 2; - case PCH_DEVFN_GSPI2: - return 3; - } - return -1; -} diff --git a/src/soc/intel/icelake/systemagent.c b/src/soc/intel/icelake/systemagent.c deleted file mode 100644 index 4a24d3911f..0000000000 --- a/src/soc/intel/icelake/systemagent.c +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <intelblocks/systemagent.h> -#include <soc/iomap.h> -#include <soc/systemagent.h> - -/* - * SoC implementation - * - * Add all known fixed memory ranges for Host Controller/Memory - * controller. - */ -void soc_add_fixed_mmio_resources(struct device *dev, int *index) -{ - static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, - "PCIEXBAR" }, - { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, - { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, - { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, - { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, - { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, - /* - * PMC pci device gets hidden from PCI bus due to Silicon - * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with - * SA resources to ensure that PMCBAR falls under PCI reserved - * memory range. - * - * Note: Don't add any more resource with same offset 0x10 - * under this device space. - */ - { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, - "PMCBAR" }, - }; - - sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, - ARRAY_SIZE(soc_fixed_resources)); -} - -/* - * SoC implementation - * - * Perform System Agent Initialization during Ramstage phase. - */ -void soc_systemagent_init(struct device *dev) -{ - /* Enable Power Aware Interrupt Routing */ - enable_power_aware_intr(); - - /* Enable BIOS Reset CPL */ - enable_bios_reset_cpl(); -} - -uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) -{ - switch (capid0_a_ddrsz) { - case 1: - return 8192; - case 2: - return 4096; - case 3: - return 2048; - default: - return 65536; - } -} diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c deleted file mode 100644 index 9946880263..0000000000 --- a/src/soc/intel/icelake/uart.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <commonlib/helpers.h> -#include <soc/pci_devs.h> - -const unsigned int uart_devices[] = { - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2, -}; - -const int uart_devices_size = ARRAY_SIZE(uart_devices); diff --git a/util/release/genrelnotes b/util/release/genrelnotes index 01eb294df4..1bbe55429d 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -379,8 +379,6 @@ get_log_dedupe "Qualcomm sdm845" "src/soc/qualcomm/sdm845" "sdm845" get_log_dedupe "Prodrive Hermes / Google Sarien / Intel coffeelake_rvp" "src/mainboard/intel/coffeelake_rvp src/mainboard/google/sarien src/mainboard/prodrive/hermes" get_log_dedupe "Intel Coffeelake" "soc/intel/coffeelake" -get_log_dedupe "Intel Icelake" "src/soc/intel/icelake src/mainboard/intel/icelake_rvp" "icelake" - get_log_dedupe "Cavium" "src/soc/cavium src/mainboard/cavium src/mainboard/opencellular/elgon " get_log_dedupe "Scaleway Tagada" "src/mainboard/scaleway/tagada" "tagada" |