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-rw-r--r--src/soc/intel/common/block/fast_spi/fast_spi.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 5ff0872a4f..ae4abc8ff1 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -240,6 +240,12 @@ void fast_spi_cache_bios_region(void)
if (!bios_size)
return;
+ /* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will
+ * cause memory type conflict when setting memory type to write
+ * protection, so limit the cached bios region to be no more than 16MB.
+ * */
+ bios_size = MIN(bios_size, 16 * MiB);
+
/* Round to power of two */
alignment = 1UL << (log2_ceil(bios_size));
bios_size = ALIGN_UP(bios_size, alignment);