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-rw-r--r--src/cpu/amd/agesa/family14/model_14_init.c8
-rw-r--r--src/cpu/amd/agesa/family15tn/model_15_init.c8
-rw-r--r--src/cpu/amd/agesa/family16kb/model_16_init.c8
-rw-r--r--src/cpu/amd/pi/00730F01/model_16_init.c8
-rw-r--r--src/cpu/intel/haswell/haswell_init.c4
-rw-r--r--src/cpu/intel/model_2065x/model_2065x_init.c15
-rw-r--r--src/cpu/intel/model_206ax/model_206ax_init.c15
-rw-r--r--src/soc/amd/stoneyridge/mca.c12
-rw-r--r--src/soc/intel/common/block/cpu/cpulib.c5
9 files changed, 11 insertions, 72 deletions
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 76c8521761..9539c3deef 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -15,9 +15,7 @@
static void model_14_init(struct device *dev)
{
- u8 i;
msr_t msr;
- unsigned int num_banks;
int msrno;
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
@@ -59,11 +57,7 @@ static void model_14_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
- num_banks = mca_get_bank_count();
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
+ mca_clear_status();
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 883bd59228..9d4da761c6 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -18,9 +18,7 @@ static void model_15_init(struct device *dev)
{
printk(BIOS_DEBUG, "Model 15 Init.\n");
- u8 i;
msr_t msr;
- unsigned int num_banks;
int msrno;
unsigned int cpu_idx;
#if CONFIG(LOGICAL_CPUS)
@@ -58,11 +56,7 @@ static void model_15_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
- num_banks = mca_get_bank_count();
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
+ mca_clear_status();
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index f945f80ce1..9fadc7e3e3 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -17,9 +17,7 @@ static void model_16_init(struct device *dev)
{
printk(BIOS_DEBUG, "Model 16 Init.\n");
- u8 i;
msr_t msr;
- unsigned int num_banks;
int msrno;
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
@@ -56,11 +54,7 @@ static void model_16_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
- num_banks = mca_get_bank_count();
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
+ mca_clear_status();
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 3c78c095d0..a5a8064737 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -20,9 +20,7 @@ static void model_16_init(struct device *dev)
{
printk(BIOS_DEBUG, "Model 16 Init.\n");
- u8 i;
msr_t msr;
- unsigned int num_banks;
u32 siblings;
/*
@@ -41,11 +39,7 @@ static void model_16_init(struct device *dev)
x86_mtrr_check();
/* zero the machine check error status registers */
- num_banks = mca_get_bank_count();
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
+ mca_clear_status();
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 29c663e2e7..2c6384c4e3 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -527,12 +527,10 @@ static void configure_mca(void)
for (i = 0; i < num_banks; i++)
wrmsr(IA32_MC_CTL(i), msr);
- msr.lo = msr.hi = 0;
/* TODO(adurbin): This should only be done on a cold boot. Also, some
* of these banks are core vs package scope. For now every CPU clears
* every bank. */
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
+ mca_clear_status();
}
/* All CPUs including BSP will run the following function. */
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index fe5ac56e65..f70d7b2f5f 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -73,24 +73,13 @@ static void set_max_ratio(void)
((perf_ctl.lo >> 8) & 0xff) * IRONLAKE_BCLK);
}
-static void configure_mca(void)
-{
- msr_t msr;
- int i;
- const unsigned int num_banks = mca_get_bank_count();
-
- msr.lo = msr.hi = 0;
- /* This should only be done on a cold boot */
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
-}
-
static void model_2065x_init(struct device *cpu)
{
char processor_name[49];
/* Clear out pending MCEs */
- configure_mca();
+ /* This should only be done on a cold boot */
+ mca_clear_status();
/* Print processor name */
fill_processor_name(processor_name);
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 541cb3bc67..09cad24b8b 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -297,18 +297,6 @@ unsigned int smbios_processor_external_clock(void)
return SANDYBRIDGE_BCLK;
}
-static void configure_mca(void)
-{
- msr_t msr;
- int i;
- const unsigned int num_banks = mca_get_bank_count();
-
- msr.lo = msr.hi = 0;
- /* This should only be done on a cold boot */
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
-}
-
static void model_206ax_report(void)
{
static const char *const mode[] = {"NOT ", ""};
@@ -340,7 +328,8 @@ static void model_206ax_init(struct device *cpu)
{
/* Clear out pending MCEs */
- configure_mca();
+ /* This should only be done on a cold boot */
+ mca_clear_status();
/* Print infos */
model_206ax_report();
diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c
index 0773101a29..e0c2791c2e 100644
--- a/src/soc/amd/stoneyridge/mca.c
+++ b/src/soc/amd/stoneyridge/mca.c
@@ -186,18 +186,8 @@ static void mca_check_all_banks(void)
}
}
-static void mca_clear_errors(void)
-{
- const unsigned int num_banks = mca_get_bank_count();
- const msr_t msr = {.lo = 0, .hi = 0};
-
- /* Zero all machine check error status registers */
- for (unsigned int i = 0 ; i < num_banks ; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
-}
-
void check_mca(void)
{
mca_check_all_banks();
- mca_clear_errors();
+ mca_clear_status();
}
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index a245824821..93725132b2 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -336,17 +336,14 @@ uint32_t cpu_get_max_turbo_ratio(void)
void mca_configure(void)
{
- msr_t msr;
int i;
const unsigned int num_banks = mca_get_bank_count();
printk(BIOS_DEBUG, "Clearing out pending MCEs\n");
- msr.lo = msr.hi = 0;
+ mca_clear_status();
for (i = 0; i < num_banks; i++) {
- /* Clear the machine check status */
- wrmsr(IA32_MC_STATUS(i), msr);
/* Initialize machine checks */
wrmsr(IA32_MC_CTL(i),
(msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 14:08:37 +0000