diff options
| -rw-r--r-- | src/mainboard/google/guybrush/bootblock.c | 28 | ||||
| -rw-r--r-- | src/mainboard/google/guybrush/verstage.c | 13 |
2 files changed, 23 insertions, 18 deletions
diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index cd27632498..5857d85b1b 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -2,12 +2,15 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/espi.h> +#include <amdblocks/lpc.h> #include <bootblock_common.h> #include <baseboard/variants.h> #include <console/console.h> #include <delay.h> #include <device/pci_ops.h> +#include <soc/lpc.h> #include <soc/pci_devs.h> +#include <soc/southbridge.h> #include <timer.h> #define FC350_PCIE_INIT_DELAY_US (20 * USECS_PER_MSEC) @@ -31,12 +34,13 @@ void bootblock_mainboard_early_init(void) size_t base_num_gpios, override_num_gpios; const struct soc_amd_gpio *base_gpios, *override_gpios; - dword = pci_read_config32(SOC_LPC_DEV, 0x78); - dword &= 0xFFFFF9F3; - dword |= 0x200; - pci_write_config32(SOC_LPC_DEV, 0x78, dword); - pci_write_config32(SOC_LPC_DEV, 0x44, 0); - pci_write_config32(SOC_LPC_DEV, 0x48, 0); + dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); + dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ0_PD_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); + dword |= LPC_LDRQ0_PD_EN; + pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); + + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, 0); + pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, 0); if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) return; @@ -53,13 +57,13 @@ void bootblock_mainboard_early_init(void) stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US); printk(BIOS_DEBUG, "Bootblock configure eSPI\n"); - dword = pm_read32(0x90); - dword |= 1 << 16; - pm_write32(0x90, dword); + dword = pm_read32(PM_SPI_PAD_PU_PD); + dword |= PM_ESPI_CS_USE_DATA2; + pm_write32(PM_SPI_PAD_PU_PD, dword); - dword = pm_read32(0x74); - dword |= 3 << 10; - pm_write32(0x74, dword); + dword = pm_read32(PM_ACPI_CONF); + dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; + pm_write32(PM_ACPI_CONF, dword); } void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c index aaaaf038de..a8c162f59b 100644 --- a/src/mainboard/google/guybrush/verstage.c +++ b/src/mainboard/google/guybrush/verstage.c @@ -5,6 +5,7 @@ #include <arch/io.h> #include <baseboard/variants.h> #include <security/vboot/vboot_common.h> +#include <soc/southbridge.h> static void setup_gpio(void) { @@ -29,12 +30,12 @@ void verstage_mainboard_early_init(void) if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { uint32_t dword; printk(BIOS_DEBUG, "Verstage configure eSPI\n"); - dword = pm_io_read32(0x90); - dword |= 1 << 16; - pm_io_write32(0x90, dword); + dword = pm_io_read32(PM_SPI_PAD_PU_PD); + dword |= PM_ESPI_CS_USE_DATA2; + pm_io_write32(PM_SPI_PAD_PU_PD, dword); - dword = pm_io_read32(0x74); - dword |= 3 << 10; - pm_io_write32(0x74, dword); + dword = pm_io_read32(PM_ACPI_CONF); + dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; + pm_io_write32(PM_ACPI_CONF, dword); } } |