diff options
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.lds | 17 | ||||
| -rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 1 | ||||
| -rw-r--r-- | src/cpu/amd/dualcore/dualcore.c | 90 | ||||
| -rw-r--r-- | src/cpu/x86/16bit/entry16.lds | 1 | ||||
| -rw-r--r-- | src/cpu/x86/32bit/reset32.inc | 10 | ||||
| -rw-r--r-- | src/cpu/x86/32bit/reset32.lds | 14 | ||||
| -rw-r--r-- | src/cpu/x86/car/cache_as_ram.lds | 21 |
7 files changed, 21 insertions, 133 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.lds b/src/cpu/amd/car/cache_as_ram.lds deleted file mode 100644 index 5cca0bb283..0000000000 --- a/src/cpu/amd/car/cache_as_ram.lds +++ /dev/null @@ -1,17 +0,0 @@ -/* - * init sections to place code running with cache as ram. - * - * 2004 by Stefan Reinauer <stepan@openbios.org> - */ - -SECTIONS { - .init . : { - _init = .; - *(.init.text); - *(.init.rodata); - *(.init.rodata.*); - . = ALIGN(16); - _einit = .; - } - -} diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index ee89a55588..24ea8da5e6 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -1,6 +1,7 @@ /* 2005.6 by yhlu * 2006.3 yhlu add copy data from CAR to ram */ +#include <arch/stages.h> #include "cpu/amd/car/disable_cache_as_ram.c" static inline void print_debug_pcar(const char *strval, uint32_t val) diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 68b595a539..99a0dbbb8b 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -70,95 +70,5 @@ static inline void start_other_cores(void) } } -#if CONFIG_USE_DCACHE_RAM == 0 -static void do_k8_init_and_stop_secondaries(void) -{ - struct node_core_id id; - device_t dev; - unsigned apicid; - unsigned max_siblings; - msr_t msr; - - /* Skip this if there was a built in self test failure */ - - if (is_cpu_pre_e0()) { - id.nodeid = lapicid() & 0x7; - id.coreid = 0; - } else { - /* Which cpu are we on? */ - id = get_node_core_id_x(); - - /* Set NB_CFG_MSR - * Linux expect the core to be in the least signficant bits. - */ - msr = rdmsr(NB_CFG_MSR); - msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo - wrmsr(NB_CFG_MSR, msr); - } - - /* For now assume all cpus have the same number of siblings */ - max_siblings = (cpuid_ecx(0x80000008) & 0xff) + 1; - - /* Enable extended apic ids */ - device_t dev_f0 = PCI_DEV(0, 0x18+id.nodeid, 0); - unsigned val = pci_read_config32(dev_f0, 0x68); - val |= (1 << 18) | (1 << 17); - pci_write_config32(dev_f0, 0x68, val); - - /* Set the lapicid */ - #if (CONFIG_ENABLE_APIC_EXT_ID == 1) - unsigned initial_apicid = get_initial_apicid(); - #if CONFIG_LIFT_BSP_APIC_ID == 0 - if( initial_apicid != 0 ) // other than bsp - #endif - { - /* use initial apic id to lift it */ - uint32_t dword = lapic_read(LAPIC_ID); - dword &= ~(0xff<<24); - dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24); - - lapic_write(LAPIC_ID, dword); - } - - #if CONFIG_LIFT_BSP_APIC_ID == 1 - bsp_apicid += CONFIG_APIC_ID_OFFSET; - #endif - - #endif - - - /* Remember the cpuid */ - if (id.coreid == 0) { - dev = PCI_DEV(0, 0x18 + id.nodeid, 2); - pci_write_config32(dev, 0x9c, cpuid_eax(1)); - } - - /* Maybe call distinguish_cpu_resets only on the last core? */ - distinguish_cpu_resets(id.nodeid); - if (!boot_cpu()) { - stop_this_cpu(); - } -} - -static void k8_init_and_stop_secondaries(void) -{ - /* This doesn't work with Cache As Ram because it messes with - the MTRR state, which breaks the init detection. - do_k8_init_and_stop_secondaries should be usable by CAR code. - */ - - int init_detected; - init_detected = early_mtrr_init_detected(); - amd_early_mtrr_init(); - - enable_lapic(); - init_timer(); - if (init_detected) { - asm volatile ("jmp __cpu_reset"); - } - do_k8_init_and_stop_secondaries(); -} - -#endif diff --git a/src/cpu/x86/16bit/entry16.lds b/src/cpu/x86/16bit/entry16.lds index db37e66302..0580f0e803 100644 --- a/src/cpu/x86/16bit/entry16.lds +++ b/src/cpu/x86/16bit/entry16.lds @@ -1,2 +1 @@ gdtptr16_offset = gdtptr16 & 0xffff; - _start_offset = _start & 0xffff; diff --git a/src/cpu/x86/32bit/reset32.inc b/src/cpu/x86/32bit/reset32.inc deleted file mode 100644 index 42c68cc770..0000000000 --- a/src/cpu/x86/32bit/reset32.inc +++ /dev/null @@ -1,10 +0,0 @@ - .section ".reset" - .code16 -.globl reset_vector -reset_vector: - - . = 0x8; - .code32 - jmp protected_start - - .previous diff --git a/src/cpu/x86/32bit/reset32.lds b/src/cpu/x86/32bit/reset32.lds deleted file mode 100644 index 1afb215c41..0000000000 --- a/src/cpu/x86/32bit/reset32.lds +++ /dev/null @@ -1,14 +0,0 @@ -/* - * _ROMTOP : The top of the rom used where we - * need to put the reset vector. - */ - -SECTIONS { - _ROMTOP = CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10; - . = _ROMTOP; - .reset (.): { - *(.reset) - . = 15 ; - BYTE(0x00); - } -} diff --git a/src/cpu/x86/car/cache_as_ram.lds b/src/cpu/x86/car/cache_as_ram.lds index 7f1b373dba..b08a08828f 100644 --- a/src/cpu/x86/car/cache_as_ram.lds +++ b/src/cpu/x86/car/cache_as_ram.lds @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Stefan Reinauer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + SECTIONS { .init . : { _init = .; @@ -7,5 +27,4 @@ SECTIONS { . = ALIGN(16); _einit = .; } - } |