diff options
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/hudson.c | 8 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/hudson.h | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/lpc.c | 12 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/sm.c | 12 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/spi.c | 2 |
5 files changed, 19 insertions, 17 deletions
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 9a6df61dba..eb8ae52193 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -77,14 +77,15 @@ static void hudson_disable_usb(u8 disable) pm_write8(PM_REG_USB_ENABLE, reg8); } -void hudson_enable(device_t dev) +void hudson_enable(struct device *dev) { printk(BIOS_DEBUG, "hudson_enable()\n"); switch (dev->path.pci.devfn) { case PCI_DEVFN(0x14, 5): if (dev->enabled == 0) { // read the VENDEV ID - device_t usb_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 5)); + struct device *usb_dev = + dev_find_slot( 0, PCI_DEVFN( 0x14, 5)); u32 usb_device_id = pci_read_config32(usb_dev, 0) >> 16; u8 reg8; if (usb_device_id == PCI_DEVICE_ID_AMD_SB900_USB_20_5) { @@ -99,7 +100,8 @@ void hudson_enable(device_t dev) case PCI_DEVFN(0x14, 7): if (dev->enabled == 0) { // read the VENDEV ID - device_t sd_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 7)); + struct device *sd_dev = + dev_find_slot( 0, PCI_DEVFN( 0x14, 7)); u32 sd_device_id = pci_read_config32( sd_dev, 0) >> 16; /* turn off the SDHC controller in the PM reg */ u8 reg8; diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index c89f6825f7..165d33f777 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -79,7 +79,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); #else -void hudson_enable(device_t dev); +void hudson_enable(struct device *dev); #endif /* __PRE_RAM__ */ #endif /* __SMM__ */ diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 7ada832339..132a3335af 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -31,11 +31,11 @@ #include "hudson.h" #include "pci_devs.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -86,7 +86,7 @@ static void lpc_init(device_t dev) setup_i8254 (); } -static void hudson_lpc_read_resources(device_t dev) +static void hudson_lpc_read_resources(struct device *dev) { struct resource *res; @@ -134,7 +134,7 @@ static void hudson_lpc_set_resources(struct device *dev) * @param dev the device whose children's resources are to be enabled * */ -static void hudson_lpc_enable_childrens_resources(device_t dev) +static void hudson_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -174,7 +174,7 @@ static void hudson_lpc_enable_childrens_resources(device_t dev) reg_var[0] = pci_read_config16(dev, 0x64); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -313,7 +313,7 @@ static void hudson_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); } -static void hudson_lpc_enable_resources(device_t dev) +static void hudson_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); hudson_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index 74367a75aa..1b6f5ae99f 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -76,12 +76,12 @@ * HUDSON enables SATA by default in SMBUS Control. */ -static void sm_init(device_t dev) +static void sm_init(struct device *dev) { setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); } -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device *dev) { u32 device; struct resource *res; @@ -95,7 +95,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device *dev, u8 val) { u32 device; struct resource *res; @@ -109,7 +109,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device *dev, u8 address) { u32 device; struct resource *res; @@ -123,7 +123,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) { u32 device; struct resource *res; @@ -143,7 +143,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void hudson_sm_read_resources(device_t dev) +static void hudson_sm_read_resources(struct device *dev) { } diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 22951ab9f0..de6792f692 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -79,7 +79,7 @@ static void execute_command(void) void spi_init(void) { - device_t dev; + struct device *dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; |