diff options
| -rw-r--r-- | src/device/Kconfig | 2 | ||||
| -rw-r--r-- | src/device/dram/Kconfig | 57 | ||||
| -rw-r--r-- | src/device/dram/Makefile.inc | 19 |
3 files changed, 76 insertions, 2 deletions
diff --git a/src/device/Kconfig b/src/device/Kconfig index c0ba3d1614..60ee04709b 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -953,4 +953,6 @@ config XHCI_UTILS help Provides xHCI utility functions. +source "src/device/dram/Kconfig" + endmenu diff --git a/src/device/dram/Kconfig b/src/device/dram/Kconfig new file mode 100644 index 0000000000..7bb1dab50d --- /dev/null +++ b/src/device/dram/Kconfig @@ -0,0 +1,57 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Short-term plan: Start adding 'USE_' and "NO_" options to each chip. +# +# Long-term plan: Every SoC or chipset should select the memory types they +# use. When they all select their memory, the 'no_' options can be removed +# and the defaults for all memory types can be set to n. + +config NO_DDR5 + bool + +config NO_LPDDR4 + bool + +config NO_DDR4 + bool + +config NO_DDR3 + bool + +config NO_DDR2 + bool + +config USE_DDR5 + bool + default n if NO_DDR5 + default y + help + system supports DDR5 memory + +config USE_LPDDR4 + bool + default n if NO_LPDDR4 + default y + help + system supports LPDDR4 memory + +config USE_DDR4 + bool + default n if NO_DDR4 + default y + help + system supports DDR4 memory + +config USE_DDR3 + bool + default n if NO_DDR3 + default y + help + system supports DDR3 memory + +config USE_DDR2 + bool + default n if NO_DDR2 + default y + help + system supports DDR2 memory diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index 31dfb91d7f..fc472ea711 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1,3 +1,18 @@ -romstage-y += ddr5.c lpddr4.c ddr4.c ddr3.c ddr2.c ddr_common.c -ramstage-y += ddr5.c lpddr4.c ddr4.c ddr3.c ddr2.c ddr_common.c spd.c +romstage-y += ddr_common.c +ramstage-y += ddr_common.c spd.c + +romstage-$(CONFIG_USE_DDR5) += ddr5.c +ramstage-$(CONFIG_USE_DDR5) += ddr5.c + +romstage-$(CONFIG_USE_LPDDR4) += lpddr4.c +ramstage-$(CONFIG_USE_LPDDR4) += lpddr4.c + +romstage-$(CONFIG_USE_DDR4) += ddr4.c +ramstage-$(CONFIG_USE_DDR4) += ddr4.c + +romstage-$(CONFIG_USE_DDR3) += ddr3.c +ramstage-$(CONFIG_USE_DDR3) += ddr3.c + +romstage-$(CONFIG_USE_DDR2) += ddr2.c +ramstage-$(CONFIG_USE_DDR2) += ddr2.c |