diff options
| -rw-r--r-- | src/arch/arm64/armv8/cache.c | 4 | ||||
| -rw-r--r-- | src/arch/arm64/armv8/secmon_loader.c | 3 | ||||
| -rw-r--r-- | src/arch/arm64/include/armv8/arch/cache.h | 11 |
3 files changed, 15 insertions, 3 deletions
diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index c1dba9259a..d568f261ed 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -144,7 +144,5 @@ void dcache_mmu_enable(void) void cache_sync_instructions(void) { flush_dcache_all(); /* includes trailing DSB (in assembly) */ - iciallu(); /* includes BPIALLU (architecturally) */ - dsb(); - isb(); + icache_invalidate_all(); /* includdes leading DSB and trailing ISB. */ } diff --git a/src/arch/arm64/armv8/secmon_loader.c b/src/arch/arm64/armv8/secmon_loader.c index 7a6e3ee738..d3eda185d1 100644 --- a/src/arch/arm64/armv8/secmon_loader.c +++ b/src/arch/arm64/armv8/secmon_loader.c @@ -22,6 +22,7 @@ * and parameter location for the rmodule. */ +#include <arch/cache.h> #include <arch/lib_helpers.h> #include <arch/secmon.h> #include <arch/spintable.h> @@ -106,6 +107,8 @@ static void secmon_start(void *arg) scr |= SCR_NS; raw_write_scr_el3(scr); + /* Invalidate instruction cache. Necessary for non-BSP. */ + icache_invalidate_all(); entry(p); } diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 6ee6101256..27fe8e0595 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -86,4 +86,15 @@ void cache_sync_instructions(void); /* tlb invalidate all */ void tlb_invalidate_all(void); +/* Invalidate all of the instruction cache for PE to PoU. */ +static inline void icache_invalidate_all(void) +{ + __asm__ __volatile__( + "dsb sy\n\t" + "ic iallu\n\t" + "dsb sy\n\t" + "isb\n\t" + : : : "memory"); +} + #endif /* ARM_ARM64_CACHE_H */ |