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-rw-r--r--src/drivers/ati/ragexl/mach64.h24
-rw-r--r--src/drivers/ati/ragexl/xlinit.c18
2 files changed, 21 insertions, 21 deletions
diff --git a/src/drivers/ati/ragexl/mach64.h b/src/drivers/ati/ragexl/mach64.h
index 3acbef45dd..354ae2ba0d 100644
--- a/src/drivers/ati/ragexl/mach64.h
+++ b/src/drivers/ati/ragexl/mach64.h
@@ -101,7 +101,7 @@
#define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
#define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
-#define CONFIG_PANEL_LG 0x0074 /* Dword offset 0_1D */
+#define CFG_PANEL_LG 0x0074 /* Dword offset 0_1D */
/* General I/O Control */
#define GP_IO 0x0078 /* Dword offset 0_1E */
@@ -120,8 +120,8 @@
#define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */
/* Configuration */
-#define CONFIG_STAT1 0x0094 /* Dword offset 0_25 */
-#define CONFIG_STAT2 0x0098 /* Dword offset 0_26 */
+#define CFG_STAT1 0x0094 /* Dword offset 0_25 */
+#define CFG_STAT2 0x0098 /* Dword offset 0_26 */
/* Bus Control */
#define BUS_CNTL 0x00A0 /* Dword offset 0_28 */
@@ -158,9 +158,9 @@
#define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */
/* Configuration */
-#define CONFIG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */
-#define CONFIG_CHIP_ID 0x00E0 /* Dword offset 0_38 */
-#define CONFIG_STAT0 0x00E4 /* Dword offset 0_39 */
+#define CFG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */
+#define CFG_CHIP_ID 0x00E0 /* Dword offset 0_38 */
+#define CFG_STAT0 0x00E4 /* Dword offset 0_39 */
/* Test and Debug */
#define CRC_SIG 0x00E8 /* Dword offset 0_3A */
@@ -726,17 +726,17 @@
#define VCLK2_POST 0x30
#define VCLK3_POST 0xC0
-/* CONFIG_CNTL register constants */
+/* CFG_CNTL register constants */
#define APERTURE_4M_ENABLE 1
#define APERTURE_8M_ENABLE 2
#define VGA_APERTURE_ENABLE 4
-/* CONFIG_STAT0 register constants (GX, CX) */
+/* CFG_STAT0 register constants (GX, CX) */
#define CFG_BUS_TYPE 0x00000007
#define CFG_MEM_TYPE 0x00000038
#define CFG_INIT_DAC_TYPE 0x00000e00
-/* CONFIG_STAT0 register constants (CT, ET, VT) */
+/* CFG_STAT0 register constants (CT, ET, VT) */
#define CFG_MEM_TYPE_xT 0x00000007
#define ISA 0
@@ -815,7 +815,7 @@
#define PCI_ATI_VENDOR_ID 0x1002
-/* CONFIG_CHIP_ID register constants */
+/* CFG_CHIP_ID register constants */
#define CFG_CHIP_TYPE 0x0000FFFF
#define CFG_CHIP_CLASS 0x00FF0000
#define CFG_CHIP_REV 0xFF000000
@@ -824,7 +824,7 @@
#define CFG_CHIP_MINOR 0xC0000000
-/* Chip IDs read from CONFIG_CHIP_ID */
+/* Chip IDs read from CFG_CHIP_ID */
/* mach64GX family */
#define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */
@@ -1113,7 +1113,7 @@
#define CRTC2_DISPLAY_DIS 0x00000400
/* LCD register indices */
-#define CONFIG_PANEL 0x00
+#define CFG_PANEL 0x00
#define LCD_GEN_CTRL 0x01
#define DSTN_CONTROL 0x02
#define HFB_PITCH_ADDR 0x03
diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c
index 19291809af..3427b0e934 100644
--- a/src/drivers/ati/ragexl/xlinit.c
+++ b/src/drivers/ati/ragexl/xlinit.c
@@ -210,7 +210,7 @@ static int atyfb_xl_init(struct fb_info_aty *info)
union aty_pll pll;
const struct xl_card_cfg_t * card = &card_cfg[xl_card];
- aty_st_8(CONFIG_STAT0, 0x85, info);
+ aty_st_8(CFG_STAT0, 0x85, info);
mdelay(10);
/*
@@ -269,7 +269,7 @@ static int atyfb_xl_init(struct fb_info_aty *info)
aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, info);
aty_st_le32(CRTC_GEN_CNTL, 0x04000200, info);
- aty_st_le16(CONFIG_STAT0, 0x0020, info);
+ aty_st_le16(CFG_STAT0, 0x0020, info);
aty_st_le32(MEM_CNTL, 0x10151A33, info);
aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, info);
aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, info);
@@ -292,7 +292,7 @@ static int atyfb_xl_init(struct fb_info_aty *info)
aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info);
}
- aty_st_le16(CONFIG_STAT0, 0x00A4, info);
+ aty_st_le16(CFG_STAT0, 0x00A4, info);
mdelay(10);
aty_st_8(BUS_CNTL+1, 0xA0, info);
@@ -330,7 +330,7 @@ static int atyfb_xl_init(struct fb_info_aty *info)
aty_st_le32(MEM_CNTL, card->mem_cntl, info);
aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, info);
- aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, info);
+ aty_st_8(CFG_STAT0, 0xA0 | card->mem_type, info);
aty_st_pll(PLL_YCLK_CNTL, 0x01, info);
mdelay(15);
@@ -348,12 +348,12 @@ static int atyfb_xl_init(struct fb_info_aty *info)
// disable extended register block
aty_st_8(BUS_CNTL+3, 0x73, info);
- aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, info);
+ aty_st_8(CFG_STAT0, 0x80 | card->mem_type, info);
// disable display requests, disable CRTC
aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
// disable mapping registers in VGA aperture
- aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, info) & ~0x04, info);
+ aty_st_8(CFG_CNTL, aty_ld_8(CFG_CNTL, info) & ~0x04, info);
mdelay(50);
// enable display requests, enable CRTC
aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
@@ -556,7 +556,7 @@ static void ati_ragexl_init(struct device *dev)
printk(BIOS_DEBUG, "ati_regbase = 0x%p, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);
#endif
- chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
+ chip_id = aty_ld_le32(CFG_CHIP_ID, info);
type = chip_id & CFG_CHIP_TYPE;
rev = (chip_id & CFG_CHIP_REV)>>24;
for (j = 0; j < ARRAY_SIZE(aty_chips); j++)
@@ -598,7 +598,7 @@ found:
#if CONFIG_CONSOLE_BTEXT
- info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07);
+ info->ram_type = (aty_ld_le32(CFG_STAT0, info) & 0x07);
info->ref_clk_per = 1000000000000ULL/14318180;
xtal = "14.31818";
@@ -672,7 +672,7 @@ found:
#endif
if (M64_HAS(MAGIC_VRAM_SIZE)) {
- if (aty_ld_le32(CONFIG_STAT1, info) & 0x40000000)
+ if (aty_ld_le32(CFG_STAT1, info) & 0x40000000)
info->total_vram += 0x400000;
}
#if 0
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 18:25:31 +0000