diff options
| -rw-r--r-- | src/mainboard/digitallogic/adl855pc/Config.lb | 34 | ||||
| -rw-r--r-- | src/mainboard/digitallogic/adl855pc/auto.c | 14 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c | 20 | ||||
| -rw-r--r-- | targets/digitallogic/adl855pc/Config.lb | 6 |
4 files changed, 64 insertions, 10 deletions
diff --git a/src/mainboard/digitallogic/adl855pc/Config.lb b/src/mainboard/digitallogic/adl855pc/Config.lb index 237a1d957a..fb2ba53ba4 100644 --- a/src/mainboard/digitallogic/adl855pc/Config.lb +++ b/src/mainboard/digitallogic/adl855pc/Config.lb @@ -202,7 +202,9 @@ end ## ## Setup RAM ## +mainboardinit cpu/p6/enable_mmx_sse.inc mainboardinit ./auto.inc +mainboardinit cpu/p6/disable_mmx_sse.inc ## ## Include the secondary Configuration files @@ -224,6 +226,38 @@ northbridge intel/i855pm "i855pm" # pci 0:12.0 register "enable_usb" = "0" register "enable_native_ide" = "0" + register "enable_usb" = "0" + register "enable_native_ide" = "0" + superio winbond/w83627hf link 1 + pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + pnp 2e.6 off # CIR + pnp 2e.7 off # GAME_MIDI_GIPO1 + pnp 2e.8 off # GPIO2 + pnp 2e.9 off # GPIO3 + pnp 2e.a off # ACPI + pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + register "com1" = "{1}" + # register "com1" = "{1, 0, 0x3f8, 4}" + # register "lpt" = "{1}" + end end end diff --git a/src/mainboard/digitallogic/adl855pc/auto.c b/src/mainboard/digitallogic/adl855pc/auto.c index 305f5c359c..6e6b2cd944 100644 --- a/src/mainboard/digitallogic/adl855pc/auto.c +++ b/src/mainboard/digitallogic/adl855pc/auto.c @@ -1,4 +1,5 @@ #define ASSEMBLY 1 + #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -26,6 +27,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + static void hard_reset(void) { outb(0x0e, 0x0cf9); @@ -60,7 +62,7 @@ static void main(void) static const struct mem_controller memctrl[] = { { .d0 = PCI_DEV(0, 0, 0), - .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 }, + .channel0 = { (0xa<<3)|0, 0 }, }, }; @@ -73,14 +75,14 @@ static void main(void) uart_init(); console_init(); -#if 1 +#if 0 print_pci_devices(); #endif if(!bios_reset_detected()) { enable_smbus(); #if 1 -// dump_spd_registers(&memctrl[0]); - dump_smbus_registers(); + dump_spd_registers(&memctrl[0]); + // dump_smbus_registers(); #endif memreset_setup(); @@ -102,10 +104,10 @@ static void main(void) } #endif -#if 1 +#if 0 dump_pci_devices(); #endif -#if 1 +#if 0 dump_pci_device(PCI_DEV(0, 0, 0)); #endif diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c b/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c index de721a1e83..05ad2d7b5c 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c +++ b/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c @@ -46,6 +46,21 @@ static inline void smbus_delay(void) outb(0x80, 0x80); } +static int smbus_wait_until_active(void) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if ((val & 1)) { + break; + } + } while(--loops); + return loops?0:-4; +} + static int smbus_wait_until_ready(void) { unsigned long loops; @@ -112,7 +127,10 @@ static int smbus_read_byte(unsigned device, unsigned address) /* start a byte read, with interrupts disabled */ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - + /* poll for it to start */ + if (smbus_wait_until_active() < 0) { + return -4; + } /* poll for transaction completion */ if (smbus_wait_until_done() < 0) { diff --git a/targets/digitallogic/adl855pc/Config.lb b/targets/digitallogic/adl855pc/Config.lb index 09bdbb7ca4..58d1bcf8f2 100644 --- a/targets/digitallogic/adl855pc/Config.lb +++ b/targets/digitallogic/adl855pc/Config.lb @@ -52,8 +52,8 @@ option TTYS0_BAUD=115200 option CONFIG_CHIP_CONFIGURE=1 -option MAXIMUM_CONSOLE_LOGLEVEL=7 -option DEFAULT_CONSOLE_LOGLEVEL=7 +option MAXIMUM_CONSOLE_LOGLEVEL=9 +option DEFAULT_CONSOLE_LOGLEVEL=9 option CONFIG_CONSOLE_SERIAL8250=1 option CPU_FIXUP=1 @@ -61,7 +61,7 @@ option CONFIG_UDELAY_TSC=0 option i686=1 option i586=1 option INTEL_PPRO_MTRR=1 -option ROM_SIZE=256*1024 +option ROM_SIZE=1024*1024 option HAVE_OPTION_TABLE=1 option CONFIG_ROM_STREAM=1 |