diff options
37 files changed, 48 insertions, 37 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index ac1b45d4eb..ab8787c32c 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -47,7 +47,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index 3a55f9e1f3..7f84adb5b7 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS select RT8168_SET_LED_MODE select MAINBOARD_HAS_LPC_TPM +config DISABLE_HECI1_AT_PRE_BOOT + default y + config MAINBOARD_DIR default "asrock/h110m" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index aed9184e99..a45127c0b3 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -101,9 +101,6 @@ chip soc/intel/skylake device pci 15.3 off end # I2C #3 device pci 16.0 on # Management Engine Interface 1 subsystemid 0x1849 0xa131 - - # FIXME: does not match devicetree! - register "HeciEnabled" = "0" end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index db4d1acb75..d22f57419a 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -60,9 +60,7 @@ chip soc/intel/skylake register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left end device ref thermal on end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref sata on register "SataSalpSupport" = "0" # Ports diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 50738f49d9..0fb05a1ef7 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -13,6 +13,9 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_GMA_HAVE_VBT select VPD +config DISABLE_HECI1_AT_PRE_BOOT + default y + config CBFS_SIZE default 0x00900000 diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 023ace9224..05bcc12257 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ @@ -224,6 +223,7 @@ chip soc/intel/skylake device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 device pci 17.0 on end # SATA device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210 diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 007cbc7287..5e1b2f7ea5 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -24,6 +24,9 @@ config BOARD_SPECIFIC_OPTIONS select SYSTEM_TYPE_CONVERTIBLE select HAVE_SPD_IN_CBFS +config DISABLE_HECI1_AT_PRE_BOOT + default y + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index c7310052db..1e9ffd9255 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -43,7 +43,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index afb28310e9..cf5dd19a16 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -24,6 +24,9 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ select RT8168_SUPPORT_LEGACY_VPD_MAC select RT8168_SET_LED_MODE +config DISABLE_HECI1_AT_PRE_BOOT + default y + config BOARD_GOOGLE_FIZZ select BOARD_GOOGLE_BASEBOARD_FIZZ diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index ceca5f14ce..5ecc77bc77 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -74,7 +74,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 04a48f7275..8ed327e9f7 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -21,6 +21,9 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS select SOC_INTEL_SKYLAKE select SYSTEM_TYPE_LAPTOP +config DISABLE_HECI1_AT_PRE_BOOT + default y + config BOARD_GOOGLE_ASUKA select BOARD_GOOGLE_BASEBOARD_GLADOS select DRIVERS_GENERIC_MAX98357A diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index a200cfb8bd..9a3e619499 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -42,7 +42,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 4a19f865b3..87f39339ab 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -99,6 +99,9 @@ config BOARD_GOOGLE_SORAKA if BOARD_GOOGLE_BASEBOARD_POPPY +config DISABLE_HECI1_AT_PRE_BOOT + default y + config CHROMEOS_WIFI_SAR bool depends on CHROMEOS diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 39b7d9f9e0..d26f6bd28a 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -50,7 +50,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 4d145e18e7..db4aeebb9f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -38,7 +38,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 6d7541e4d7..7609e004cc 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -37,7 +37,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 068a031f1d..b8a1812751 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -38,7 +38,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index e4e01585bd..03336f2e47 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -43,7 +43,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index ff06d6acfe..c6c2d3df60 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -50,7 +50,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 9be000f0d3..5c347924df 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -38,7 +38,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/hp/280_g2/Kconfig b/src/mainboard/hp/280_g2/Kconfig index df3f626e9f..0db753d2cf 100644 --- a/src/mainboard/hp/280_g2/Kconfig +++ b/src/mainboard/hp/280_g2/Kconfig @@ -16,6 +16,9 @@ config BOARD_SPECIFIC_OPTIONS select SPD_READ_BY_WORD select SUPERIO_ITE_COMMON_PRE_RAM +config DISABLE_HECI1_AT_PRE_BOOT + default y + config MAINBOARD_DIR default "hp/280_g2" diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 2abf8329f6..6b60ac46ea 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -31,6 +31,9 @@ config BOARD_INTEL_KBLRVP11 if BOARD_INTEL_KBLRVP_COMMON +config DISABLE_HECI1_AT_PRE_BOOT + default y + config VBOOT select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index e17c8b71f3..bae6198118 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -20,7 +20,6 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "HeciEnabled" = "0" register "IoBufferOwnership" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 85f9e54d82..22fffb0203 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -21,6 +21,9 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_SKYLAKE select HAVE_SPD_IN_CBFS +config DISABLE_HECI1_AT_PRE_BOOT + default y + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index ba4835eb25..deb9f38c7a 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -25,7 +25,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index decbb9688a..5d16d22875 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -16,6 +16,9 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION +config DISABLE_HECI1_AT_PRE_BOOT + default y + config MAINBOARD_DIR default "intel/saddlebrook" diff --git a/src/mainboard/kontron/bsl6/Kconfig b/src/mainboard/kontron/bsl6/Kconfig index 9fae364316..78e81c4573 100644 --- a/src/mainboard/kontron/bsl6/Kconfig +++ b/src/mainboard/kontron/bsl6/Kconfig @@ -15,6 +15,9 @@ config BOARD_KONTRON_BSL6_COMMON select MAINBOARD_HAS_LIBGFXINIT select DRIVERS_I2C_NCT7802Y +config DISABLE_HECI1_AT_PRE_BOOT + default y + config BOARD_KONTRON_BSL6 select BOARD_KONTRON_BSL6_COMMON select HAVE_ACPI_RESUME diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index d047f76349..39c2e33a28 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -46,7 +46,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index a264c6b276..feb8b9f1e3 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "IslVrCmd" = "2" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 4c6f6a8ade..e20a002716 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -18,6 +18,9 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL if BOARD_PURISM_BASEBOARD_LIBREM_SKL +config DISABLE_HECI1_AT_PRE_BOOT + default y + config VARIANT_DIR default "librem13" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM13_V4 default "librem15" if BOARD_PURISM_LIBREM15_V3 || BOARD_PURISM_LIBREM15_V4 diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index dfa894b3d4..ef898b2a19 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -52,7 +52,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 3d311a3dd4..3b2343b92c 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -31,7 +31,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index eb4a65e750..10606559bd 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -18,6 +18,9 @@ config BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES +config DISABLE_HECI1_AT_PRE_BOOT + default y + config MAINBOARD_FAMILY string default "Supermicro_X11_LGA1151_SERIES" diff --git a/src/mainboard/system76/kbl-u/Kconfig b/src/mainboard/system76/kbl-u/Kconfig index a714bb88fa..cb45bf39c7 100644 --- a/src/mainboard/system76/kbl-u/Kconfig +++ b/src/mainboard/system76/kbl-u/Kconfig @@ -18,6 +18,9 @@ config BOARD_SPECIFIC_OPTIONS select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP +config DISABLE_HECI1_AT_PRE_BOOT + default y + config MAINBOARD_DIR default "system76/kbl-u" diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a04869990d..5c1cc6113f 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -410,11 +410,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) tconfig->PowerLimit4 = 0; /* * To disable HECI, the Psf needs to be left unlocked - * by FSP till end of post sequence. Based on the devicetree + * by FSP till end of post sequence. Based on the config * setting, we set the appropriate PsfUnlock policy in FSP, * do the changes and then lock it back in coreboot during finalize. */ - tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; + tconfig->PchSbAccessUnlock = CONFIG(DISABLE_HECI1_AT_PRE_BOOT); const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; tconfig->PchLockDownBiosInterface = lockdown_by_fsp; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 08d5d0f398..12a6ae9762 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -395,11 +395,6 @@ struct soc_intel_skylake_config { * 3 = GT unsliced, 4 = GT sliced */ struct vr_config domain_vr_config[NUM_VR_DOMAINS]; - /* - * HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS - */ - u8 HeciEnabled; /* * Enable VR specific mailbox command diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 83bd3ae8a2..733f037975 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -44,15 +44,11 @@ static void pch_disable_heci(void) static void pch_finalize_script(struct device *dev) { - config_t *config; - tco_lockdown(); /* Display me status before we hide it */ intel_me_status(); - config = config_of(dev); - /* * Set low maximum temp value used for dynamic thermal sensor * shutdown consideration. @@ -62,8 +58,8 @@ static void pch_finalize_script(struct device *dev) */ pch_thermal_configuration(); - /* we should disable Heci1 based on the devicetree policy */ - if (config->HeciEnabled == 0) + /* we should disable Heci1 based on the config */ + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) pch_disable_heci(); /* Hide p2sb device as the OS must not change BAR0. */ |