diff options
| -rw-r--r-- | src/northbridge/intel/haswell/native_raminit/raminit_native.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/thermal.c | 64 |
4 files changed, 67 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c index ef61d4ee09..dd1f1ec14e 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c @@ -16,6 +16,7 @@ static bool early_init_native(int s3resume) /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/ const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check(); + early_thermal_init(); early_usb_init(); if (!CONFIG(INTEL_LYNXPOINT_LP)) diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 14bba2e1b0..5874c4f1de 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -35,7 +35,7 @@ bootblock-y += early_pch.c romstage-y += early_usb.c early_me.c me_status.c early_pch.c romstage-y += pmutil.c -romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c +romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index d8fcf52a7d..5fa9edbcb1 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -115,6 +115,7 @@ enum pch_platform_type { void pch_dmi_setup_physical_layer(void); void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm); void early_usb_init(void); +void early_thermal_init(void); void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); void usb_ehci_disable(pci_devfn_t dev); diff --git a/src/southbridge/intel/lynxpoint/thermal.c b/src/southbridge/intel/lynxpoint/thermal.c new file mode 100644 index 0000000000..e71969ea0c --- /dev/null +++ b/src/southbridge/intel/lynxpoint/thermal.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <types.h> + +#define TBARB_TEMP 0x40000000 + +#define THERMAL_DEV PCI_DEV(0, 0x1f, 6) + +/* Early thermal init, it may need to be done prior to giving ME its memory */ +void early_thermal_init(void) +{ + /* Program address for temporary BAR */ + pci_write_config32(THERMAL_DEV, 0x40, TBARB_TEMP); + pci_write_config32(THERMAL_DEV, 0x44, 0); + + /* Activate temporary BAR */ + pci_or_config32(THERMAL_DEV, 0x40, 1); + + /* + * BWG section 17.3.1 says: + * + * ### Initializing Lynx Point Thermal Sensors ### + * + * The System BIOS must perform the following steps to initialize the Lynx + * Point thermal subsystem device, D31:F6. The System BIOS is required to + * repeat this process on a resume from Sx. BIOS may enable any or all of + * the registers below based on OEM's platform configuration. Intel does + * not recommend a value on some of the registers, since each platform has + * different temperature trip points and one may enable a trip to cause an + * SMI while another platform would cause an interrupt instead. + * + * The recommended flow for enabling thermal sensor is by setting up various + * temperature trip points first, followed by enabling the desired trip + * alert method and then enable the actual sensors from TSEL registers. + * If this flow is not followed, software will need to take special care + * to handle false events during setting up those registers. + */ + + /* Step 1: Program CTT */ + write16p(TBARB_TEMP + 0x10, 0x0154); + + /* Step 2: Clear trip status from TSS and TAS */ + write8p(TBARB_TEMP + 0x06, 0xff); + write8p(TBARB_TEMP + 0x80, 0xff); + + /* Step 3: Program TSGPEN and TSPIEN to zero */ + write8p(TBARB_TEMP + 0x84, 0x00); + write8p(TBARB_TEMP + 0x82, 0x00); + + /* + * Step 4: If thermal reporting to an EC over SMBus is supported, + * then write 0x01 to TSREL, else leave at default. + */ + write8p(TBARB_TEMP + 0x0a, 0x01); + + /* Disable temporary BAR */ + pci_and_config32(THERMAL_DEV, 0x40, ~1); + + /* Clear temporary BAR address */ + pci_write_config32(THERMAL_DEV, 0x40, 0); +} |