diff options
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/fw_config.c | 38 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/gpio.c | 4 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/overridetree.cb | 4 |
3 files changed, 7 insertions, 39 deletions
diff --git a/src/mainboard/google/brya/variants/craask/fw_config.c b/src/mainboard/google/brya/variants/craask/fw_config.c index d6679108f8..937e90d086 100644 --- a/src/mainboard/google/brya/variants/craask/fw_config.c +++ b/src/mainboard/google/brya/variants/craask/fw_config.c @@ -50,39 +50,16 @@ static const struct pad_config stylus_disable_pads[] = { static const struct pad_config nvme_disable_pads[] = { /* B4 : SSD_PERST_L */ PAD_NC_LOCK(GPP_B4, NONE, LOCK_CONFIG), + /* D7 : SSD_CLKREQ_ODL */ + PAD_NC(GPP_D7, NONE), /* D11 : EN_PP3300_SSD */ PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG), /* E17 : SSD_PLN_L */ PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), - /* - * Note: don't disable GPP_D6 = SSD_CLKREQ_ODL, since this is used as - * WWAN_EN on LTE variants. - */ -}; - -/* - * GPP_D6 is used as WWAN_EN on LTE variants and SSD_CLKREQ_ODL on NVMe - * variants (there is no craask variant supporting both LTE and NVMe). - * In craask/gpio.c, it's set to WWAN_EN since this needs to be done in - * bootblock. So we override it to SSD_CLKREQ_ODL here for NVMe variants. - */ -static const struct pad_config nvme_enable_pads[] = { - /* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), }; void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { - /* - * Since GPP_D6 is used as WWAN_EN on LTE variants and SSD_CLKREQ_ODL on - * NVMe variants, we don't support both together. If there's a variant - * using both in the future, this GPIO handling will need to be updated. - */ - if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE)) && - fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { - printk(BIOS_ERR, "LTE and NVMe together is not supported on craask\n"); - } - if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { printk(BIOS_INFO, "Disable LTE-related GPIO pins on craask.\n"); gpio_padbased_override(padbased_table, lte_disable_pads, @@ -107,16 +84,7 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) ARRAY_SIZE(stylus_disable_pads)); } - if (!fw_config_is_provisioned() || - fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { - /* - * Note: this must be done after lte_disable_pads, otherwise - * GPP_D6 will be disabled again. - */ - printk(BIOS_INFO, "Enable NVMe SSD GPIO pins.\n"); - gpio_padbased_override(padbased_table, nvme_enable_pads, - ARRAY_SIZE(nvme_enable_pads)); - } else { + if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { printk(BIOS_INFO, "Disable NVMe SSD GPIO pins.\n"); gpio_padbased_override(padbased_table, nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads)); diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c index 5d0db35caa..bebc8d2138 100644 --- a/src/mainboard/google/brya/variants/craask/gpio.c +++ b/src/mainboard/google/brya/variants/craask/gpio.c @@ -13,8 +13,8 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* D6 : WWAN_EN */ PAD_CFG_GPO(GPP_D6, 1, DEEP), - /* D7 : WLAN_CLKREQ_ODL */ - PAD_NC(GPP_D7, NONE), + /* D7 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* D11 : EN_PP3300_SSD */ PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), /* E17 : SSD_PLN_L */ diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 1a733fb282..19cf876eb9 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -447,10 +447,10 @@ chip soc/intel/alderlake probe SD_CARD SD_GL9750S end device ref pcie_rp9 on - # Enable NVMe SSD PCIe 9-12 using clk 1 + # Enable NVMe SSD PCIe 9-12 using clk 2 register "pch_pcie_rp[PCH_RP(9)]" = "{ .clk_src = 1, - .clk_req = 1, + .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end |