diff options
| -rw-r--r-- | src/southbridge/amd/cimx_wrapper/sb800/cfg.h | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx_wrapper/sb800/late.c | 12 | ||||
| -rw-r--r-- | src/vendorcode/amd/cimx/sb800/EC.c | 4 | ||||
| -rw-r--r-- | src/vendorcode/amd/cimx/sb800/SATA.c | 4 | ||||
| -rw-r--r-- | src/vendorcode/amd/cimx/sb800/SBTYPE.h | 8 |
5 files changed, 16 insertions, 16 deletions
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/cfg.h b/src/southbridge/amd/cimx_wrapper/sb800/cfg.h index e89daca381..581fc661ea 100644 --- a/src/southbridge/amd/cimx_wrapper/sb800/cfg.h +++ b/src/southbridge/amd/cimx_wrapper/sb800/cfg.h @@ -100,7 +100,7 @@ * @breif INCHIP Sata Controller */ #ifndef SATA_CONTROLLER - #define SATA_CONTROLLER ENABLED + #define SATA_CONTROLLER CIMX_OPTION_ENABLED #endif /** @@ -202,7 +202,7 @@ * @def GPP_CONTROLLER */ #ifndef GPP_CONTROLLER - #define GPP_CONTROLLER ENABLED + #define GPP_CONTROLLER CIMX_OPTION_ENABLED #endif /** diff --git a/src/southbridge/amd/cimx_wrapper/sb800/late.c b/src/southbridge/amd/cimx_wrapper/sb800/late.c index e375b23dd8..de1637a0c5 100644 --- a/src/southbridge/amd/cimx_wrapper/sb800/late.c +++ b/src/southbridge/amd/cimx_wrapper/sb800/late.c @@ -21,6 +21,7 @@ #include <device/device.h> /* device_t */ #include <device/pci.h> /* device_operations */ #include <device/pci_ids.h> +#include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <console/console.h> /* printk */ #include "lpc.h" /* lpc_read_resources */ @@ -328,13 +329,13 @@ static void sb800_enable(device_t dev) switch (dev->path.pci.devfn) { case (0x11 << 3) | 0: /* 0:11.0 SATA */ if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataController = ENABLED; + sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; if (1 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. else if (0 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { - sb_config->SATAMODE.SataMode.SataController = DISABLED; + sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; } sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY @@ -352,11 +353,10 @@ static void sb800_enable(device_t dev) case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ { - u8 byte; u32 ioapic_base; printk(BIOS_INFO, "sm_init().\n"); - ioapic_base = 0xFEC00000; + ioapic_base = IO_APIC_ADDR; clear_ioapic(ioapic_base); /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) @@ -374,9 +374,9 @@ static void sb800_enable(device_t dev) case (0x14 << 3) | 1: /* 0:14:1 IDE */ if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED; + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED; } else { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED; } sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY break; diff --git a/src/vendorcode/amd/cimx/sb800/EC.c b/src/vendorcode/amd/cimx/sb800/EC.c index 220424f905..633d251624 100644 --- a/src/vendorcode/amd/cimx/sb800/EC.c +++ b/src/vendorcode/amd/cimx/sb800/EC.c @@ -71,7 +71,7 @@ ecPowerOnInit ( RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1 - if ( pConfig->BuildParameters.EcKbd == ENABLED) { + if ( pConfig->BuildParameters.EcKbd == CIMX_OPTION_ENABLED) { //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3); @@ -83,7 +83,7 @@ ecPowerOnInit ( RWEC8 (0x30, 0x00, 0x01); } - if ( pConfig->BuildParameters.EcChannel0 == ENABLED) { + if ( pConfig->BuildParameters.EcChannel0 == CIMX_OPTION_ENABLED) { //Logical device 0x03 RWEC8 (0x07, 0x00, 0x03); RWEC8 (0x60, 0x00, 0x00); diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c index 0f85f3a190..5777d3adfe 100644 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ b/src/vendorcode/amd/cimx/sb800/SATA.c @@ -470,7 +470,7 @@ sataInitAfterPciEnum ( if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) { // RIAD or AHCI - if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) { + if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) { RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0); RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F); // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. @@ -631,7 +631,7 @@ sataInitLatePost ( //Enable write access to pci header, pm capabilities RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); -// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) { +// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) { RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7); // } sataBar5setting (pConfig, &ddBar5); diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h index 4ba7140f7f..ea3e6f6c42 100644 --- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h @@ -1093,13 +1093,13 @@ typedef unsigned int CIM_STATUS; #pragma pack (pop) /** - * DISABLED - Define disable in module + * CIMX_OPTION_DISABLED - Define disable in module */ -#define DISABLED 0 +#define CIMX_OPTION_DISABLED 0 /** - * ENABLED - Define enable in module + * CIMX_OPTION_ENABLED - Define enable in module */ -#define ENABLED 1 +#define CIMX_OPTION_ENABLED 1 // mov al, code // out 80h, al |