diff options
| -rw-r--r-- | src/drivers/intel/fsp1_1/after_raminit.S | 13 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/romstage.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/common/Kconfig | 7 | ||||
| -rw-r--r-- | src/soc/intel/common/util.c | 26 | ||||
| -rw-r--r-- | src/soc/intel/common/util.h | 8 |
5 files changed, 48 insertions, 13 deletions
diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index eb99157959..122c0bf03e 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -87,6 +87,13 @@ * +0: Number of variable MTRRs to clear */ +#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS) + push %esp + call soc_set_mtrrs + + /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */ + movl %eax, %esp +#else /* Clear all of the variable MTRRs. */ popl %ebx movl $MTRR_PHYS_BASE(0), %ecx @@ -129,6 +136,8 @@ dec %ebx jmp 2b 2: +#endif /* CONFIG_SOC_SETS_MTRRS */ + post_code(0x39) /* And enable cache again after setting MTRRs. */ @@ -138,11 +147,15 @@ post_code(0x3a) +#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS) + call soc_enable_mtrrs +#else /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr orl $MTRR_DEF_TYPE_EN, %eax wrmsr +#endif /* CONFIG_SOC_SETS_MTRRS */ post_code(0x3b) diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 4683f5e5a2..d07dc375c8 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -88,4 +88,11 @@ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd); void soc_pre_ram_init(struct romstage_params *params); +/* + * Set the MTRRs using the data on the stack from setup_stack_and_mtrrs. + * Return a new top_of_stack value which removes the setup_stack_and_mtrrs data. + */ +asmlinkage void *soc_set_mtrrs(void *top_of_stack); +asmlinkage void soc_enable_mtrrs(void); + #endif /* _COMMON_ROMSTAGE_H_ */ diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 028e915e56..8b68aad46c 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -41,6 +41,13 @@ config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE bool default n +config SOC_SETS_MTRRS + bool + default n + help + The SoC needs uses different access methods for reading and writing + the MTRRs. Use SoC specific routines to handle the MTRR access. + config MMA bool "enable MMA (Memory Margin Analysis) support" default n diff --git a/src/soc/intel/common/util.c b/src/soc/intel/common/util.c index dc3f139694..74ce9ff28f 100644 --- a/src/soc/intel/common/util.c +++ b/src/soc/intel/common/util.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,7 +15,6 @@ #include <arch/cpu.h> #include <console/console.h> -#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <soc/intel/common/util.h> #include <stddef.h> @@ -25,12 +24,12 @@ uint32_t soc_get_variable_mtrr_count(uint64_t *msr) union { uint64_t u64; msr_t s; - } mttrcap; + } mtrrcap; - mttrcap.s = rdmsr(MTRR_CAP_MSR); + mtrrcap.s = soc_mtrr_read(MTRR_CAP_MSR); if (msr != NULL) - *msr = mttrcap.u64; - return mttrcap.u64 & MTRR_CAP_VCNT; + *msr = mtrrcap.u64; + return mtrrcap.u64 & MTRR_CAP_VCNT; } static const char *soc_display_mtrr_type(uint32_t type) @@ -84,7 +83,7 @@ static void soc_display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address, msr_t s; } msr; - msr.s = rdmsr(msr_reg); + msr.s = soc_mtrr_read(msr_reg); printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x1000); } @@ -97,7 +96,7 @@ static void soc_display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address, msr_t s; } msr; - msr.s = rdmsr(msr_reg); + msr.s = soc_mtrr_read(msr_reg); printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x4000); } @@ -109,7 +108,7 @@ static void soc_display_64k_mtrr(void) msr_t s; } msr; - msr.s = rdmsr(MTRR_FIX_64K_00000); + msr.s = soc_mtrr_read(MTRR_FIX_64K_00000); printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64); soc_display_mtrr_fixed_types(msr.u64, 0, 0x10000); } @@ -137,12 +136,13 @@ static void soc_display_mtrr_def_type(void) msr_t s; } msr; - msr.s = rdmsr(MTRR_DEF_TYPE_MSR); + msr.s = soc_mtrr_read(MTRR_DEF_TYPE_MSR); printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_DEF_TYPE:%s%s %s\n", msr.u64, (msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "", (msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "", - soc_display_mtrr_type((uint32_t)(msr.u64 & MTRR_DEF_TYPE_MASK))); + soc_display_mtrr_type((uint32_t)(msr.u64 & + MTRR_DEF_TYPE_MASK))); } static void soc_display_variable_mtrr(uint32_t msr_reg, int index, @@ -160,8 +160,8 @@ static void soc_display_variable_mtrr(uint32_t msr_reg, int index, msr_t s; } msr_m; - msr_a.s = rdmsr(msr_reg); - msr_m.s = rdmsr(msr_reg + 1); + msr_a.s = soc_mtrr_read(msr_reg); + msr_m.s = soc_mtrr_read(msr_reg + 1); if (msr_m.u64 & MTRR_PHYS_MASK_VALID) { base_address = (msr_a.u64 & 0xfffffffffffff000ULL) & address_mask; diff --git a/src/soc/intel/common/util.h b/src/soc/intel/common/util.h index 8c41151160..7d05e47c1d 100644 --- a/src/soc/intel/common/util.h +++ b/src/soc/intel/common/util.h @@ -17,9 +17,17 @@ #define _INTEL_COMMON_UTIL_H_ #include <arch/cpu.h> +#include <cpu/x86/msr.h> #include <stdint.h> asmlinkage void soc_display_mtrrs(void); uint32_t soc_get_variable_mtrr_count(uint64_t *msr); +#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS) +msr_t soc_mtrr_read(unsigned long index); +void soc_mtrr_write(unsigned long index, msr_t msr); +#else +#define soc_mtrr_read rdmsr +#define soc_mtrr_write wrmsr +#endif /* CONFIG_SOC_SETS_MTRRS */ #endif /* _INTEL_COMMON_UTIL_H_ */ |