diff options
| -rw-r--r-- | src/arch/ppc64/include/arch/io.h | 2 | ||||
| -rw-r--r-- | src/arch/ppc64/rom_media.c | 5 | ||||
| -rw-r--r-- | src/arch/ppc64/stages.c | 13 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-power9/memlayout.ld | 27 |
4 files changed, 36 insertions, 11 deletions
diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index 6dc0a84b6c..cfaae33f60 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -8,7 +8,9 @@ /* Set MSB to 1 to ignore HRMOR */ #define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000 #define LPCHC_IO_SPACE 0xD0010000 +#define FLASH_IO_SPACE 0xFC000000 #define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE) +#define FLASH_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + FLASH_IO_SPACE) #define MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR 0x800603FC00000000 /* Enforce In-order Execution of I/O */ diff --git a/src/arch/ppc64/rom_media.c b/src/arch/ppc64/rom_media.c index 7d849e4cdb..2fd47669a8 100644 --- a/src/arch/ppc64/rom_media.c +++ b/src/arch/ppc64/rom_media.c @@ -1,11 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <boot_device.h> -/* This assumes that the CBFS resides at 0x0, which is true for the default - * configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(FLASH_BASE_ADDR, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { diff --git a/src/arch/ppc64/stages.c b/src/arch/ppc64/stages.c index 20ed723bf5..01b9efaba8 100644 --- a/src/arch/ppc64/stages.c +++ b/src/arch/ppc64/stages.c @@ -13,10 +13,23 @@ #include <cbmem.h> #include <arch/stages.h> +#include <cpu/power/spr.h> void stage_entry(uintptr_t stage_arg) { +#if ENV_RAMSTAGE + uint64_t hrmor; +#endif + if (!ENV_ROMSTAGE_OR_BEFORE) _cbmem_top_ptr = stage_arg; + +#if ENV_RAMSTAGE + hrmor = read_spr(SPR_HRMOR); + asm volatile("sync; isync" ::: "memory"); + write_spr(SPR_HRMOR, 0); + asm volatile("or 1,1,%0; slbia 7; sync; isync" :: "r"(hrmor) : "memory"); +#endif + main(); } diff --git a/src/mainboard/emulation/qemu-power9/memlayout.ld b/src/mainboard/emulation/qemu-power9/memlayout.ld index 42e388951f..8209433020 100644 --- a/src/mainboard/emulation/qemu-power9/memlayout.ld +++ b/src/mainboard/emulation/qemu-power9/memlayout.ld @@ -10,14 +10,25 @@ SECTIONS BOOTBLOCK(0, 32K) - ROMSTAGE(0xf00000, 1M) - STACK(0x1000000, 32K) - RAMSTAGE(0x1008000, 1M) + ROMSTAGE(0x1f00000, 1M) - FMAP_CACHE(0x1108000, 4K) - CBFS_MCACHE(0x1109000, 8K) - TIMESTAMP(0x110b000, 4K) - CBFS_CACHE(0x110c000, 512K) - PRERAM_CBMEM_CONSOLE(0x118c000, 128K) +#if !ENV_RAMSTAGE + STACK(0x2000000, 32K) +#endif + FMAP_CACHE(0x2108000, 4K) + CBFS_MCACHE(0x2109000, 8K) + TIMESTAMP(0x210b000, 4K) + CBFS_CACHE(0x210c000, 512K) + PRERAM_CBMEM_CONSOLE(0x218c000, 128K) + + /* By default all memory addresses are affected by the value of HRMOR + * (Hypervisor Real Mode Offset Register) which is ORed to them. HRMOR + * has initial value of 0x8000000 in QEMU and is changed to 0 in + * ramstage. This means that before ramstage 0 actually points to + * 0x8000000. */ +#if ENV_RAMSTAGE + STACK(0xa000000, 32K) +#endif + RAMSTAGE(0xa008000, 1M) } |