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-rw-r--r--src/mainboard/asrock/b85m_pro4/romstage.c10
-rw-r--r--src/mainboard/asrock/h81m-hds/romstage.c6
-rw-r--r--src/mainboard/google/beltino/romstage.c6
-rw-r--r--src/mainboard/google/slippy/romstage.c35
-rw-r--r--src/mainboard/google/slippy/variant.h5
-rw-r--r--src/mainboard/google/slippy/variants/falco/romstage.c18
-rw-r--r--src/mainboard/google/slippy/variants/leon/romstage.c17
-rw-r--r--src/mainboard/google/slippy/variants/peppy/romstage.c23
-rw-r--r--src/mainboard/google/slippy/variants/wolf/romstage.c20
-rw-r--r--src/mainboard/hp/folio_9480m/romstage.c6
-rw-r--r--src/mainboard/intel/baskingridge/romstage.c10
-rw-r--r--src/mainboard/lenovo/t440p/romstage.c6
-rw-r--r--src/mainboard/msi/h81m-p33/romstage.c6
-rw-r--r--src/mainboard/supermicro/x10slm-f/romstage.c10
-rw-r--r--src/northbridge/intel/haswell/raminit.h12
-rw-r--r--src/northbridge/intel/haswell/romstage.c38
16 files changed, 114 insertions, 114 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c
index 1c17fcb909..7a4e402d91 100644
--- a/src/mainboard/asrock/b85m_pro4/romstage.c
+++ b/src/mainboard/asrock/b85m_pro4/romstage.c
@@ -17,12 +17,12 @@ void mainboard_config_rcba(void)
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
-void mb_get_spd_map(uint8_t spd_map[4])
+void mb_get_spd_map(struct spd_info *spdi)
{
- spd_map[0] = 0xa0;
- spd_map[1] = 0xa2;
- spd_map[2] = 0xa4;
- spd_map[3] = 0xa6;
+ spdi->addresses[0] = 0xa0;
+ spdi->addresses[1] = 0xa2;
+ spdi->addresses[2] = 0xa4;
+ spdi->addresses[3] = 0xa6;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index 16b1500bd6..58f9697162 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -17,10 +17,10 @@ void mainboard_config_rcba(void)
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
-void mb_get_spd_map(uint8_t spd_map[4])
+void mb_get_spd_map(struct spd_info *spdi)
{
- spd_map[0] = 0xa0;
- spd_map[2] = 0xa4;
+ spdi->addresses[0] = 0xa0;
+ spdi->addresses[2] = 0xa4;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index dda2edc8d5..b69fb933b3 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -40,10 +40,10 @@ void mainboard_config_rcba(void)
RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */
}
-void mb_get_spd_map(uint8_t spd_map[4])
+void mb_get_spd_map(struct spd_info *spdi)
{
- spd_map[0] = 0xa0;
- spd_map[2] = 0xa4;
+ spdi->addresses[0] = 0xa0;
+ spdi->addresses[2] = 0xa4;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index 89eaab986b..d5bf1023e9 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -1,12 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <cbfs.h>
-#include <console/console.h>
-#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
-#include <string.h>
-#include <types.h>
#include "variant.h"
@@ -45,31 +40,9 @@ void mainboard_config_rcba(void)
RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */
}
-void mb_get_spd_map(uint8_t spd_map[4])
+void mb_get_spd_map(struct spd_info *spdi)
{
- spd_map[0] = 0xff;
- spd_map[2] = 0xff;
-}
-
-unsigned int fill_spd_for_index(uint8_t spd[], unsigned int spd_index)
-{
- uint8_t *spd_file;
- size_t spd_file_len;
-
- printk(BIOS_DEBUG, "SPD index %d\n", spd_index);
- spd_file = cbfs_map("spd.bin", &spd_file_len);
- if (!spd_file)
- die("SPD data not found.");
-
- if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
- printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
- spd_index = 0;
- }
-
- if (spd_file_len < SPD_LEN)
- die("Missing SPD data.");
-
- memcpy(spd, spd_file + (spd_index * SPD_LEN), SPD_LEN);
-
- return spd_index;
+ spdi->spd_index = variant_get_spd_index();
+ spdi->addresses[0] = SPD_MEMORY_DOWN;
+ spdi->addresses[2] = variant_is_dual_channel(spdi->spd_index) ? SPD_MEMORY_DOWN : 0;
}
diff --git a/src/mainboard/google/slippy/variant.h b/src/mainboard/google/slippy/variant.h
index f1aa6ab768..d0b5476ed5 100644
--- a/src/mainboard/google/slippy/variant.h
+++ b/src/mainboard/google/slippy/variant.h
@@ -3,8 +3,9 @@
#ifndef VARIANT_H
#define VARIANT_H
-#include <stdint.h>
+#include <types.h>
-unsigned int fill_spd_for_index(uint8_t spd[], unsigned int index);
+unsigned int variant_get_spd_index(void);
+bool variant_is_dual_channel(const unsigned int spd_index);
#endif
diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c
index 05b4eb78c5..e808182274 100644
--- a/src/mainboard/google/slippy/variants/falco/romstage.c
+++ b/src/mainboard/google/slippy/variants/falco/romstage.c
@@ -6,22 +6,22 @@
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include "../../variant.h"
-/* Copy SPD data for on-board memory */
-void copy_spd(struct pei_data *peid)
+unsigned int variant_get_spd_index(void)
{
const int gpio_vector[] = {13, 9, 47, -1};
+ return get_gpios(gpio_vector);
+}
- unsigned int spd_index = fill_spd_for_index(peid->spd_data[0], get_gpios(gpio_vector));
-
+bool variant_is_dual_channel(const unsigned int spd_index)
+{
/* Index 0-2,6 are 4GB config with both CH0 and CH1
- * Index 3-5,7 are 2GB config with CH0 only
- */
+ Index 3-5,7 are 2GB config with CH0 only */
switch (spd_index) {
case 0: case 1: case 2: case 6:
- memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN);
- break;
+ return true;
case 3: case 4: case 5: case 7:
- peid->dimm_channel1_disabled = 3;
+ default:
+ return false;
}
}
diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c
index 2e5dee195e..c22e25b897 100644
--- a/src/mainboard/google/slippy/variants/leon/romstage.c
+++ b/src/mainboard/google/slippy/variants/leon/romstage.c
@@ -6,20 +6,17 @@
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include "../../variant.h"
-/* Copy SPD data for on-board memory */
-void copy_spd(struct pei_data *peid)
+unsigned int variant_get_spd_index(void)
{
const int gpio_vector[] = {13, 9, 47, -1};
+ return get_gpios(gpio_vector);
+}
- unsigned int spd_index = fill_spd_for_index(peid->spd_data[0], get_gpios(gpio_vector));
-
+bool variant_is_dual_channel(const unsigned int spd_index)
+{
/* Limiting to a single dimm for 2GB configuration
- * Identified by bit 3
- */
- if (spd_index & 0x4)
- peid->dimm_channel1_disabled = 3;
- else
- memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN);
+ Identified by bit 2 */
+ return !(spd_index & 0x4);
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c
index 12e2714b6d..dd998f00f3 100644
--- a/src/mainboard/google/slippy/variants/peppy/romstage.c
+++ b/src/mainboard/google/slippy/variants/peppy/romstage.c
@@ -9,33 +9,26 @@
#include "../../onboard.h"
#include "../../variant.h"
-/* Copy SPD data for on-board memory */
-void copy_spd(struct pei_data *peid)
+unsigned int variant_get_spd_index(void)
{
const int gpio_vector[] = {13, 9, 47, -1};
+ return get_gpios(gpio_vector);
+}
- unsigned int spd_index = fill_spd_for_index(peid->spd_data[0], get_gpios(gpio_vector));
-
+bool variant_is_dual_channel(const unsigned int spd_index)
+{
uint32_t board_version = PEPPY_BOARD_VERSION_PROTO;
google_chromeec_get_board_version(&board_version);
switch (board_version) {
case PEPPY_BOARD_VERSION_PROTO:
/* Index 0 is 2GB config with CH0 only. */
- if (spd_index == 0)
- peid->dimm_channel1_disabled = 3;
- else
- memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN);
- break;
+ return spd_index != 0;
case PEPPY_BOARD_VERSION_EVT:
default:
/* Index 0-3 are 4GB config with both CH0 and CH1.
- * Index 4-7 are 2GB config with CH0 only. */
- if (spd_index > 3)
- peid->dimm_channel1_disabled = 3;
- else
- memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN);
- break;
+ Index 4-7 are 2GB config with CH0 only. */
+ return spd_index <= 3;
}
}
diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c
index 05e128d87e..95a14a08aa 100644
--- a/src/mainboard/google/slippy/variants/wolf/romstage.c
+++ b/src/mainboard/google/slippy/variants/wolf/romstage.c
@@ -6,22 +6,22 @@
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include "../../variant.h"
-/* Copy SPD data for on-board memory */
-void copy_spd(struct pei_data *peid)
+unsigned int variant_get_spd_index(void)
{
const int gpio_vector[] = {13, 9, 47, -1};
+ return get_gpios(gpio_vector);
+}
- unsigned int spd_index = fill_spd_for_index(peid->spd_data[0], get_gpios(gpio_vector));
-
- /* Index 0-2, are 4GB config with both CH0 and CH1
- * Index 3-5, are 2GB config with CH0 only
- */
+bool variant_is_dual_channel(const unsigned int spd_index)
+{
+ /* Index 0-2 are 4GB config with both CH0 and CH1
+ Index 3-5 are 2GB config with CH0 only */
switch (spd_index) {
case 0: case 1: case 2:
- memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN);
- break;
+ return true;
case 3: case 4: case 5:
- peid->dimm_channel1_disabled = 3;
+ default:
+ return false;
}
}
diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c
index 496005d802..af3005f04c 100644
--- a/src/mainboard/hp/folio_9480m/romstage.c
+++ b/src/mainboard/hp/folio_9480m/romstage.c
@@ -17,10 +17,10 @@ void mainboard_config_rcba(void)
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
-void mb_get_spd_map(uint8_t spd_map[4])
+void mb_get_spd_map(struct spd_info *spdi)
{
- spd_map[0] = 0xa0;
- spd_map[2] = 0xa4;
+ spdi->addresses[0] = 0xa0;
+ spdi->addresses[2] = 0xa4;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index dc1f50fa32..7580799898 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -41,12 +41,12 @@ void mainboard_config_rcba(void)
RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
-void mb_get_spd_map(uint8_t spd_map[4])
+void mb_get_spd_map(struct spd_info *spdi)
{
- spd_map[0] = 0xa0;
- spd_map[1] = 0xa2;
- spd_map[2] = 0xa4;
- spd_map[3] = 0xa6;
+ spdi->addresses[0] = 0xa0;
+ spdi->addresses[1] = 0xa2;
+ spdi->addresses[2] = 0xa4;
+ spdi->addresses[3] = 0xa6;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c
index 7aca7c5351..7840a1fffa 100644
--- a/src/mainboard/lenovo/t440p/romstage.c
+++ b/src/mainboard/lenovo/t440p/romstage.c
@@ -40,10 +40,10 @@ void mb_late_romstage_setup(void)
}
}
-void mb_get_spd_map(uint8_t spd_map[4])
+void mb_get_spd_map(struct spd_info *spdi)
{
- spd_map[0] = 0xa0;
- spd_map[2] = 0xa2;
+ spdi->addresses[0] = 0xa0;
+ spdi->addresses[2] = 0xa2;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c
index 9bcb400d32..059ebdc1b6 100644
--- a/src/mainboard/msi/h81m-p33/romstage.c
+++ b/src/mainboard/msi/h81m-p33/romstage.c
@@ -17,10 +17,10 @@ void mainboard_config_rcba(void)
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
-void mb_get_spd_map(uint8_t spd_map[4])
+void mb_get_spd_map(struct spd_info *spdi)
{
- spd_map[0] = 0xa0;
- spd_map[2] = 0xa4;
+ spdi->addresses[0] = 0xa0;
+ spdi->addresses[2] = 0xa4;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index 36f79a303b..2ec993ffb3 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -17,12 +17,12 @@ void mainboard_config_rcba(void)
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
-void mb_get_spd_map(uint8_t spd_map[4])
+void mb_get_spd_map(struct spd_info *spdi)
{
- spd_map[0] = 0xa0;
- spd_map[1] = 0xa2;
- spd_map[2] = 0xa4;
- spd_map[3] = 0xa6;
+ spdi->addresses[0] = 0xa0;
+ spdi->addresses[1] = 0xa2;
+ spdi->addresses[2] = 0xa4;
+ spdi->addresses[3] = 0xa6;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h
index 6efea3e6ef..ff95a453fb 100644
--- a/src/northbridge/intel/haswell/raminit.h
+++ b/src/northbridge/intel/haswell/raminit.h
@@ -6,15 +6,19 @@
#include <stdint.h>
#include "pei_data.h"
+#define SPD_MEMORY_DOWN 0xff
+
+struct spd_info {
+ uint8_t addresses[4];
+ unsigned int spd_index;
+};
+
/* Mainboard-specific USB configuration */
extern const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS];
extern const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS];
-/* Optional function to copy SPD data for on-board memory */
-void copy_spd(struct pei_data *peid);
-
/* Mainboard callback to fill in the SPD addresses in MRC format */
-void mb_get_spd_map(uint8_t spd_map[4]);
+void mb_get_spd_map(struct spd_info *spdi);
void sdram_initialize(struct pei_data *pei_data);
void setup_sdram_meminfo(struct pei_data *pei_data);
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 48ba4767e4..f65098f6fc 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/romstage.h>
+#include <cbfs.h>
#include <console/console.h>
#include <cf9_reset.h>
#include <device/device.h>
@@ -21,10 +22,37 @@
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/me.h>
#include <string.h>
+#include <types.h>
/* Copy SPD data for on-board memory */
-void __weak copy_spd(struct pei_data *peid)
+static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi)
{
+ if (!CONFIG(HAVE_SPD_IN_CBFS))
+ return;
+
+ printk(BIOS_DEBUG, "SPD index %d\n", spdi->spd_index);
+
+ size_t spd_file_len;
+ uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len);
+
+ if (!spd_file)
+ die("SPD data not found.");
+
+ if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
+ printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+ spdi->spd_index = 0;
+ }
+
+ if (spd_file_len < SPD_LEN)
+ die("Missing SPD data.");
+
+ /* MRC only uses index 0, but coreboot uses the other indices */
+ memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_LEN), SPD_LEN);
+
+ for (size_t i = 1; i < ARRAY_SIZE(spdi->addresses); i++) {
+ if (spdi->addresses[i] == SPD_MEMORY_DOWN)
+ memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_LEN);
+ }
}
void __weak mb_late_romstage_setup(void)
@@ -98,7 +126,11 @@ void mainboard_romstage_entry(void)
pei_data.boot_mode = s3resume ? 2 : 0;
/* Obtain the SPD addresses from mainboard code */
- mb_get_spd_map(pei_data.spd_addresses);
+ struct spd_info spdi = {0};
+ mb_get_spd_map(&spdi);
+
+ for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++)
+ pei_data.spd_addresses[i] = spdi.addresses[i];
/* Calculate unimplemented DIMM slots for each channel */
pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
@@ -111,7 +143,7 @@ void mainboard_romstage_entry(void)
if (CONFIG(INTEL_TXT))
intel_txt_romstage_init();
- copy_spd(&pei_data);
+ copy_spd(&pei_data, &spdi);
sdram_initialize(&pei_data);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 05:21:03 +0000