diff options
| -rw-r--r-- | src/northbridge/amd/pi/00630F01/northbridge.c | 66 | ||||
| -rw-r--r-- | src/northbridge/amd/pi/00660F01/northbridge.c | 68 | ||||
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/northbridge.c | 68 |
3 files changed, 101 insertions, 101 deletions
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index f542495b05..fed7e53c81 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -108,7 +108,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { if (((CONFIG_CDB + nodeid) < 32) || (MAX_NODE_NUMS + CONFIG_CDB < 32)) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -147,7 +147,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for (i = 0; i < fx_devs; i++) { - device_t dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -155,7 +155,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam15_nodeid(device_t dev) +static u32 amdfam15_nodeid(struct device *dev) { unsigned busn; busn = dev->bus->secondary; @@ -186,7 +186,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, but is not usable * @retval 1 resource exists, but has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -194,7 +194,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -241,7 +241,7 @@ static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -267,7 +267,7 @@ static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -309,7 +309,7 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void read_resources(device_t dev) +static void read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -329,7 +329,7 @@ static void read_resources(device_t dev) mmconf_resource(dev, 0xc0010058); } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -380,7 +380,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -389,7 +389,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { if (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -410,7 +410,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(device_t dev) +static void set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -451,7 +451,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(device_t device) +static void northbridge_fill_ssdt_generator(struct device *device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; @@ -472,7 +472,7 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(device_t device, +static unsigned long agesa_write_acpi_tables(struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { @@ -589,7 +589,7 @@ struct chip_operations northbridge_amd_pi_00630F01_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -602,7 +602,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device *reg_dev; if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -627,7 +627,7 @@ static void domain_read_resources(device_t dev) } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device *dev) { #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) /* Must be called after PCI enumeration and resource allocation */ @@ -690,7 +690,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device *dev) { unsigned long mmio_basek; u32 pci_tolm; @@ -802,13 +802,13 @@ static struct device_operations pci_domain_ops = { .scan_bus = pci_domain_scan_bus, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -844,12 +844,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static void cpu_bus_scan(device_t dev) +static void cpu_bus_scan(struct device *dev) { struct bus *cpu_bus; - device_t dev_mc; + struct device *dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -945,7 +945,7 @@ static void cpu_bus_scan(device_t dev) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1024,14 +1024,14 @@ static void cpu_bus_scan(device_t dev) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j } } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index aa2aa1c239..39c1d9ff89 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -56,15 +56,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -80,7 +80,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -107,7 +107,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -150,7 +150,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for (i = 0; i < fx_devs; i++) { - device_t dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -158,7 +158,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam15_nodeid(device_t dev) +static u32 amdfam15_nodeid(struct device *dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -193,7 +193,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -201,7 +201,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -222,7 +222,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -243,7 +243,7 @@ static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -264,7 +264,7 @@ static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -304,7 +304,7 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void read_resources(device_t dev) +static void read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -324,7 +324,7 @@ static void read_resources(device_t dev) mmconf_resource(dev, 0xc0010058); } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -373,7 +373,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -382,7 +382,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -401,7 +401,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(device_t dev) +static void set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -447,7 +447,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(device_t device) +static void northbridge_fill_ssdt_generator(struct device *device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; @@ -468,7 +468,7 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(device_t device, +static unsigned long agesa_write_acpi_tables(struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { @@ -576,7 +576,7 @@ static const struct pci_driver family15_northbridge __pci_driver = { static void fam15_finalize(void *chip_info) { - device_t dev; + struct device *dev; u32 value; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ pci_write_config32(dev, 0xF8, 0); @@ -595,7 +595,7 @@ struct chip_operations northbridge_amd_pi_00660F01_ops = { .final = fam15_finalize, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -608,7 +608,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device *reg_dev; if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base & 0x30); } else { // io @@ -632,7 +632,7 @@ static void domain_read_resources(device_t dev) pci_domain_read_resources(dev); } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device *dev) { #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) /* Must be called after PCI enumeration and resource allocation */ @@ -694,7 +694,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device *dev) { unsigned long mmio_basek; u32 pci_tolm; @@ -804,13 +804,13 @@ static struct device_operations pci_domain_ops = { .scan_bus = pci_domain_scan_bus, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; // NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -846,12 +846,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static void cpu_bus_scan(device_t dev) +static void cpu_bus_scan(struct device *dev) { struct bus *cpu_bus; - device_t dev_mc; + struct device *dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -944,7 +944,7 @@ static void cpu_bus_scan(device_t dev) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1020,14 +1020,14 @@ static void cpu_bus_scan(device_t dev) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j } } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 6e652c0e10..456e880bc8 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -52,15 +52,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -76,7 +76,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -103,7 +103,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -146,7 +146,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for (i = 0; i < fx_devs; i++) { - device_t dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -154,7 +154,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam16_nodeid(device_t dev) +static u32 amdfam16_nodeid(struct device *dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -189,7 +189,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -197,7 +197,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -217,7 +217,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -244,7 +244,7 @@ static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -270,7 +270,7 @@ static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -312,7 +312,7 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void read_resources(device_t dev) +static void read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -332,7 +332,7 @@ static void read_resources(device_t dev) mmconf_resource(dev, 0xc0010058); } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -383,7 +383,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -392,7 +392,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -411,7 +411,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(device_t dev) +static void set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -456,7 +456,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(device_t device) +static void northbridge_fill_ssdt_generator(struct device *device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; @@ -477,7 +477,7 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(device_t device, +static unsigned long agesa_write_acpi_tables(struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { @@ -591,7 +591,7 @@ static const struct pci_driver family10_northbridge __pci_driver = { static void fam16_finalize(void *chip_info) { - device_t dev; + struct device *dev; u32 value; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ pci_write_config32(dev, 0xF8, 0); @@ -610,7 +610,7 @@ struct chip_operations northbridge_amd_pi_00730F01_ops = { .final = fam16_finalize, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -623,7 +623,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device *reg_dev; if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -646,7 +646,7 @@ static void domain_read_resources(device_t dev) pci_domain_read_resources(dev); } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device *dev) { #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) /* Must be called after PCI enumeration and resource allocation */ @@ -706,7 +706,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device *dev) { unsigned long mmio_basek; u32 pci_tolm; @@ -827,13 +827,13 @@ static struct device_operations pci_domain_ops = { .acpi_name = domain_acpi_name, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -869,12 +869,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static void cpu_bus_scan(device_t dev) +static void cpu_bus_scan(struct device *dev) { struct bus *cpu_bus; - device_t dev_mc; + struct device *dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -970,7 +970,7 @@ static void cpu_bus_scan(device_t dev) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1050,14 +1050,14 @@ static void cpu_bus_scan(device_t dev) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j } } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } |