diff options
| -rw-r--r-- | src/southbridge/intel/ibexpeak/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/lpc.c | 8 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 60af933094..5cf402c7da 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -29,6 +29,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select SOUTHBRIDGE_INTEL_COMMON + select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select HAVE_USBDEBUG_OPTIONS diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 857a53eb40..bd12944adf 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -35,6 +35,7 @@ #include "pch.h" #include "nvs.h" #include <southbridge/intel/common/pciehp.h> +#include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rcba.h> #define NMI_OFF 0 @@ -775,12 +776,18 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.addrh = 0x0; } +static const char *lpc_acpi_name(const struct device *dev) +{ + return "LPCB"; +} + static void southbridge_fill_ssdt(device_t device) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); + intel_acpi_gen_def_acpi_pirq(dev); } static void lpc_final(struct device *dev) @@ -804,6 +811,7 @@ static struct device_operations device_ops = { .enable_resources = pch_lpc_enable_resources, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_name = lpc_acpi_name, .write_acpi_tables = acpi_write_hpet, .init = lpc_init, .final = lpc_final, |