diff options
| -rw-r--r-- | src/mainboard/asrock/e350m1/devicetree.cb | 14 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx_wrapper/sb800/late.c | 31 |
2 files changed, 22 insertions, 23 deletions
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index d1e4a8b0c8..bc3bd18311 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -99,11 +99,19 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB + device pci 15.0 on end # PCIe PortA + device pci 15.1 on end # PCIe PortB device pci 15.2 off end # PCIe PortC device pci 15.3 off end # PCIe PortD - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + + # gpp_configuration options + #0000: PortA lanes[3:0] + #0001: N/A + #0010: PortA lanes[1:0], PortB lanes[3:2] + #0011: PortA lanes[1:0], PortB lane2, PortC lane3 + #0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3. + register "gpp_configuration" = "4" + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx_wrapper/sb800 # end # device pci 18.0 diff --git a/src/southbridge/amd/cimx_wrapper/sb800/late.c b/src/southbridge/amd/cimx_wrapper/sb800/late.c index 50eeb48e86..692644357a 100644 --- a/src/southbridge/amd/cimx_wrapper/sb800/late.c +++ b/src/southbridge/amd/cimx_wrapper/sb800/late.c @@ -413,16 +413,13 @@ static void sb800_enable(device_t dev) break; case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ - sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled; - return; - case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */ - sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled; - return; - case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */ - sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled; - return; - case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */ - sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled; + { + device_t device; + for (device = dev; device; device = device->next) { + if (dev->path.type != DEVICE_PATH_PCI) continue; + if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break; + sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; + } /* * GPP_CFGMODE_X4000: PortA Lanes[3:0] @@ -430,22 +427,16 @@ static void sb800_enable(device_t dev) * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 */ - if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) { - sb_config->GppLinkConfig = sb_chip->gpp_configuration; - } - - sbPcieGppEarlyInit(sb_config); + sb_config->GppLinkConfig = sb_chip->gpp_configuration; + sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; + AmdSbDispatcher(sb_config); break; + } default: break; } - /* Special setting ABCFG registers before PCI emulation. */ - abSpecialSetBeforePciEnum(sb_config); - usbDesertPll(sb_config); - //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; - //AmdSbDispatcher(sb_config); } struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = { |