4 files changed, 36 insertions, 0 deletions
diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c
index cdb2681240..ec7e4f9a0c 100644
--- a/src/mainboard/google/cherry/romstage.c
+++ b/src/mainboard/google/cherry/romstage.c
@@ -6,6 +6,7 @@
 #include <soc/mt6359p.h>
 #include <soc/pmif.h>
 #include <soc/rtc.h>
+#include <soc/scp.h>
 
 void platform_romstage_main(void)
 {
@@ -14,4 +15,5 @@ void platform_romstage_main(void)
 	mt6315_init();
 	clk_buf_init();
 	rtc_boot();
+	scp_rsi_enable();
 }
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index efd4a12d02..67ceed3603 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -27,6 +27,7 @@ romstage-y += ../common/flash_controller.c
 romstage-y += ../common/gpio.c gpio.c
 romstage-y += ../common/i2c.c i2c.c
 romstage-y += ../common/pll.c pll.c
+romstage-y += scp.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 romstage-y += ../common/timer.c timer.c
 romstage-y += ../common/uart.c
diff --git a/src/soc/mediatek/mt8195/include/soc/scp.h b/src/soc/mediatek/mt8195/include/soc/scp.h
new file mode 100644
index 0000000000..c5c552b6c5
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/scp.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8195_SCP_H
+#define SOC_MEDIATEK_MT8195_SCP_H
+
+#include <soc/addressmap.h>
+
+#define SCP_SRAM_PDN_DISABLE_VAL	0xFFFFFFFF
+
+#define REG_L1TCM_SRAM_PDN		(void *)(SCP_CFG_BASE + 0x2102C)
+
+void scp_rsi_enable(void);
+void scp_rsi_disable(void);
+#endif
diff --git a/src/soc/mediatek/mt8195/scp.c b/src/soc/mediatek/mt8195/scp.c
new file mode 100644
index 0000000000..3a3bc27b1c
--- /dev/null
+++ b/src/soc/mediatek/mt8195/scp.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/scp.h>
+
+void scp_rsi_enable(void)
+{
+	u32 val;
+
+	for (val = SCP_SRAM_PDN_DISABLE_VAL; val != 0U;) {
+		val = val >> 1;
+		write32(REG_L1TCM_SRAM_PDN, val);
+	}
+}
+
+void scp_rsi_disable(void)
+{
+	write32(REG_L1TCM_SRAM_PDN, SCP_SRAM_PDN_DISABLE_VAL);
+}