diff options
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 59efa43279..df8bd2afd3 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -48,6 +48,28 @@ chip soc/amd/cezanne # Enable S0i3 support register "s0ix_enable" = "1" + # Enable STT support + register "stt_control" = "1" + register "stt_pcb_sensor_count" = "2" + register "stt_min_limit" = "0" + register "stt_m1" = "0x0319" + register "stt_m2" = "0x01A0" + register "stt_m3" = "0" + register "stt_m4" = "0" + register "stt_m5" = "0" + register "stt_m6" = "0" + register "stt_c_apu" = "0xE99F" + register "stt_c_gpu" = "0" + register "stt_c_hs2" = "0" + register "stt_alpha_apu" = "0xCCD" + register "stt_alpha_gpu" = "0" + register "stt_alpha_hs2" = "0" + register "stt_skin_temp_apu" = "0x2D00" + register "stt_skin_temp_gpu" = "0" + register "stt_skin_temp_hs2" = "0" + register "stt_error_coeff" = "0xD" + register "stt_error_rate_coefficient" = "0x8F6" + register "system_configuration" = "2" register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | |