diff options
| -rw-r--r-- | src/soc/intel/skylake/acpi/pch.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/acpi/scs.asl | 125 | ||||
| -rw-r--r-- | src/soc/intel/skylake/acpi/serialio.asl | 29 |
3 files changed, 127 insertions, 29 deletions
diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index c72a704fc4..f2c1a16d04 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -46,6 +46,8 @@ /* SMBus 0:1f.3 */ #include "smbus.asl" +/* Storage Controllers */ +#include "scs.asl" /* USB XHCI 0:14.0 */ #include "xhci.asl" diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl new file mode 100644 index 0000000000..4eb9683c7d --- /dev/null +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Intel Storage Controllers */ + +Device (EMMC) +{ + Name (_ADR, 0x001E0004) + Name (_DDN, "eMMC Controller") + + OperationRegion (EMCR, PCI_Config, 0x00, 0x100) + Field (EMCR, DWordAcc, NoLock, Preserve) + { + Offset (0x84), /* PMECTRLSTATUS */ + D0D3, 2, /* POWERSTATE */ + Offset (0xa2), /* PG_CONFIG */ + , 2, + PGEN, 1, /* PG_ENABLE */ + } + + Method (_PS0, 0, Serialized) + { + /* Disable Power Good */ + Store (0, ^PGEN) + + /* Clear bits 31, 6, 2, 0 */ + ^^PCRA (PID_SCS, 0x600, 0x7FFFFFBA) + Sleep (2) + + /* Set bits 31, 6, 2, 0 */ + ^^PCRO (PID_SCS, 0x600, 0x80000045) + + /* Set Power State to D0 */ + Store (0, ^D0D3) + Store (^D0D3, Local0) + } + + Method (_PS3, 0, Serialized) + { + /* Enable Power Good */ + Store (1, ^PGEN) + + /* Set Power State to D0 */ + Store (3, ^D0D3) + Store (^D0D3, Local0) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } +} + +Device (SDXC) +{ + Name (_ADR, 0x001E0006) + Name (_DDN, "SD Controller") + + OperationRegion (SDCR, PCI_Config, 0x00, 0x100) + Field (SDCR, DWordAcc, NoLock, Preserve) + { + Offset (0x84), /* PMECTRLSTATUS */ + D0D3, 2, /* POWERSTATE */ + Offset (0xa2), /* PG_CONFIG */ + , 2, + PGEN, 1, /* PG_ENABLE */ + } + + Method (_PS0, 0, Serialized) + { + /* Disable Power Good */ + Store (0, ^PGEN) + + /* Clear bits 8, 7, 2, 0 */ + ^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A) + Sleep (2) + + /* Set bits 31, 6, 2, 0 */ + ^^PCRO (PID_SCS, 0x600, 0x00000185) + + /* Set Power State to D0 */ + Store (0, ^D0D3) + Store (^D0D3, Local0) + } + + Method (_PS3, 0, Serialized) + { + /* Enable Power Good */ + Store (1, ^PGEN) + + /* Set Power State to D0 */ + Store (3, ^D0D3) + Store (^D0D3, Local0) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (1) + } + } +} diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl index e57b937824..d3dca7fb14 100644 --- a/src/soc/intel/skylake/acpi/serialio.asl +++ b/src/soc/intel/skylake/acpi/serialio.asl @@ -618,32 +618,3 @@ Device (UAR2) ^^LPD3 (\SAB1, \SAEN) } } - - -Device (PEMC) -{ - Name (_ADR, 0x001E0004) - Device (CARD) - { - Name (_ADR, 0x00000008) - Method (_RMV, 0x0, NotSerialized) - { - Return (0) - } - } -} - -/* SD controller */ -Device (PSDC) -{ - Name (_ADR, 0x001E0006) - Device (CARD) - { - Name (_ADR, 0x00000008) - Method (_RMV, 0x0, NotSerialized) - { - Return (1) - } - } -} - |