diff options
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 20 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 3 |
2 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index a9a619c24e..5140369445 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -11,6 +11,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <intelblocks/cse.h> +#include <intelblocks/pmclib.h> #include <option.h> #include <security/vboot/misc.h> #include <security/vboot/vboot_common.h> @@ -1008,6 +1009,25 @@ void heci_set_to_d0i3(void) } } +void cse_control_global_reset_lock(void) +{ + /* + * As per ME BWG recommendation the BIOS should not lock down CF9GR bit during + * manufacturing and re-manufacturing environment if HFSTS1 [4] is set. Note: + * this recommendation is not applicable for CSE-Lite SKUs where BIOS should set + * CF9LOCK bit irrespectively. + * + * Other than that, make sure payload/OS can't trigger global reset. + * + * BIOS must also ensure that CF9GR is cleared and locked (Bit31 of ETR3) + * prior to transferring control to the OS. + */ + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) || cse_is_hfs1_spi_protected()) + pmc_global_reset_disable_and_lock(); + else + pmc_global_reset_enable(false); +} + #if ENV_RAMSTAGE /* diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index c2efab15fc..e67d9d8469 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -495,6 +495,9 @@ void cse_set_to_d0i3(void); /* Function sets D0I3 for all HECI devices */ void heci_set_to_d0i3(void); +/* Function performs the global reset lock */ +void cse_control_global_reset_lock(void); + /* * SoC override API to make heci1 disable using PCR. * |