diff options
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/agesawrapper.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/gpio_banks.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/lpc/lpc.c | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/pi/heapmanager.c | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/xhci.c | 1 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/smi.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 2 |
9 files changed, 0 insertions, 12 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index 8883893e52..f30fba39b1 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -25,7 +25,6 @@ AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams); void *agesawrapper_getlateinitptr(int pick); - void OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly); void amd_initcpuio(void); const void *agesawrapper_locate_module(const char name[8]); diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index b1663cf374..d5ef5d2bd3 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -136,7 +136,6 @@ enum { #define AMD_GPIO_MUX_MASK 0x03 - /* * Flags used for GPIO configuration. These provide additional information that does not go * directly into GPIO control register. These are stored in `flags` field in soc_amd_gpio. diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index deadfa2a77..107aa4af23 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -166,7 +166,6 @@ static void configure_child_lpc_windows(struct device *dev, struct device *child reg = pci_read_config32(dev, LPC_IO_PORT_DECODE_ENABLE); reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* * Be a bit relaxed, tolerate that LPC region might be bigger than * resource we try to fit, do it like this for all regions < 16 bytes. diff --git a/src/soc/amd/common/block/pi/heapmanager.c b/src/soc/amd/common/block/pi/heapmanager.c index 6f7ad7259d..699bb53431 100644 --- a/src/soc/amd/common/block/pi/heapmanager.c +++ b/src/soc/amd/common/block/pi/heapmanager.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include <amdblocks/agesawrapper.h> #include <amdblocks/BiosCallOuts.h> #include <cbmem.h> diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 6f6383d581..2c04295451 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -151,7 +151,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; @@ -159,7 +158,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; diff --git a/src/soc/amd/picasso/xhci.c b/src/soc/amd/picasso/xhci.c index 171002c0b4..97a012e03f 100644 --- a/src/soc/amd/picasso/xhci.c +++ b/src/soc/amd/picasso/xhci.c @@ -52,5 +52,4 @@ static void configure_xhci_sci(void *unused) gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources)); } - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL); diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 10e1690852..e62f235952 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -119,7 +119,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; @@ -127,7 +126,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index a58488ba3c..f7cacea37f 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -3,7 +3,6 @@ #ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ #define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ - #define SMI_GEVENTS 24 #define SCIMAPS 58 #define SCI_GPES 32 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index c6fdc60073..63ab6b4e81 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -146,7 +146,6 @@ static void set_resources(struct device *dev) struct bus *bus; struct resource *res; - /* do we need this? */ create_vga_resource(dev); @@ -232,7 +231,6 @@ static void patch_ssdt_processor_scope(acpi_header_t *ssdt) ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); } - static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) |