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-rw-r--r--src/arch/arm/armv7/cpu.S1
-rw-r--r--src/arch/arm/include/arch/header.ld2
-rw-r--r--src/arch/arm64/include/arch/header.ld2
-rw-r--r--src/arch/riscv/include/arch/header.ld2
-rw-r--r--src/arch/x86/assembly_entry.S2
-rw-r--r--src/arch/x86/include/arch/header.ld2
-rw-r--r--src/include/cbfs_glue.h1
-rw-r--r--src/soc/intel/common/block/cpu/car/cache_as_ram.S1
-rw-r--r--src/soc/nvidia/tegra210/memlayout.ld1
9 files changed, 0 insertions, 14 deletions
diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S
index bc3ebd90a0..3459fc6b08 100644
--- a/src/arch/arm/armv7/cpu.S
+++ b/src/arch/arm/armv7/cpu.S
@@ -6,7 +6,6 @@
*/
#include <arch/asm.h>
-#include <rules.h>
/*
* Dcache invalidations by set/way work by passing a [way:sbz:set:sbz:level:0]
diff --git a/src/arch/arm/include/arch/header.ld b/src/arch/arm/include/arch/header.ld
index cb69ba3fea..b1e1f9dd4b 100644
--- a/src/arch/arm/include/arch/header.ld
+++ b/src/arch/arm/include/arch/header.ld
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <rules.h>
-
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index 4f371768e4..c6d48e704f 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <rules.h>
-
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld
index d8147728ee..ddb618c293 100644
--- a/src/arch/riscv/include/arch/header.ld
+++ b/src/arch/riscv/include/arch/header.ld
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <rules.h>
-
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_ARCH(riscv)
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 6e730273f8..79d6e19502 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <rules.h>
-
/*
* This path is for stages that are post bootblock. The gdt is reloaded
* to accommodate platforms that are executing out of CAR. In order to
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index 4e78ae7198..5b380faad5 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <rules.h>
-
PHDRS
{
to_load PT_LOAD;
diff --git a/src/include/cbfs_glue.h b/src/include/cbfs_glue.h
index 652cf1b805..d4fe367d6c 100644
--- a/src/include/cbfs_glue.h
+++ b/src/include/cbfs_glue.h
@@ -6,7 +6,6 @@
#include <commonlib/region.h>
#include <console/console.h>
#include <security/vboot/misc.h>
-#include <rules.h>
/*
* This flag prevents linking hashing functions into stages where they're not required. We don't
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 1c905a4c96..552ba15bcd 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -7,7 +7,6 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/post_code.h>
-#include <rules.h>
#include <intelblocks/msr.h>
.section .init, "ax", @progbits
diff --git a/src/soc/nvidia/tegra210/memlayout.ld b/src/soc/nvidia/tegra210/memlayout.ld
index 42f2164644..d9d7070bc6 100644
--- a/src/soc/nvidia/tegra210/memlayout.ld
+++ b/src/soc/nvidia/tegra210/memlayout.ld
@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <memlayout.h>
-#include <rules.h>
#include <arch/header.ld>