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-rw-r--r--src/cpu/intel/fsp_model_206ax/finalize.c2
-rw-r--r--src/cpu/intel/fsp_model_206ax/model_206ax_init.c8
-rw-r--r--src/cpu/intel/fsp_model_406dx/model_406dx_init.c2
-rw-r--r--src/cpu/intel/haswell/bootblock.c4
-rw-r--r--src/cpu/intel/haswell/finalize.c2
-rw-r--r--src/cpu/intel/haswell/haswell_init.c4
-rw-r--r--src/cpu/intel/hyperthreading/intel_sibling.c2
-rw-r--r--src/cpu/intel/model_2065x/bootblock.c4
-rw-r--r--src/cpu/intel/model_2065x/finalize.c2
-rw-r--r--src/cpu/intel/model_2065x/model_2065x_init.c4
-rw-r--r--src/cpu/intel/model_206ax/bootblock.c4
-rw-r--r--src/cpu/intel/model_206ax/finalize.c2
-rw-r--r--src/cpu/intel/model_206ax/model_206ax_init.c8
13 files changed, 24 insertions, 24 deletions
diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c
index f027e8019f..53a6cc9c15 100644
--- a/src/cpu/intel/fsp_model_206ax/finalize.c
+++ b/src/cpu/intel/fsp_model_206ax/finalize.c
@@ -25,7 +25,7 @@
* Document Number 504790
* Revision 1.6.0, June 2012 */
-static void msr_set_bit(unsigned reg, unsigned bit)
+static void msr_set_bit(unsigned int reg, unsigned int bit)
{
msr_t msr = rdmsr(reg);
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
index e538cb209b..aedd467a9a 100644
--- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
@@ -113,8 +113,8 @@ void set_power_limits(u8 power_limit_1_time)
{
msr_t msr = rdmsr(MSR_PLATFORM_INFO);
msr_t limit;
- unsigned power_unit;
- unsigned tdp, min_power, max_power, max_time;
+ unsigned int power_unit;
+ unsigned int tdp, min_power, max_power, max_time;
u8 power_limit_1_val;
if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
@@ -251,7 +251,7 @@ static void configure_mca(void)
int cpu_get_apic_id_map(int *apic_id_map)
{
struct cpuid_result result;
- unsigned threads_per_package, threads_per_core, i, shift = 0;
+ unsigned int threads_per_package, threads_per_core, i, shift = 0;
/* Logical processors (threads) per core */
result = cpuid_ext(0xb, 0);
@@ -276,7 +276,7 @@ int cpu_get_apic_id_map(int *apic_id_map)
static void intel_cores_init(struct device *cpu)
{
struct cpuid_result result;
- unsigned threads_per_package, threads_per_core, i;
+ unsigned int threads_per_package, threads_per_core, i;
/* Logical processors (threads) per core */
result = cpuid_ext(0xb, 0);
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
index 11f5286bb0..6f1eb2cf75 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
@@ -75,7 +75,7 @@ static void configure_mca(void)
static void intel_cores_init(struct device *cpu)
{
struct cpuid_result result;
- unsigned threads_per_package, threads_per_core, i;
+ unsigned int threads_per_package, threads_per_core, i;
/* Logical processors (threads) per core */
result = cpuid_ext(0xb, 0);
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c
index 204a86bd55..0522f94c9a 100644
--- a/src/cpu/intel/haswell/bootblock.c
+++ b/src/cpu/intel/haswell/bootblock.c
@@ -31,8 +31,8 @@
#error "CPU must be paired with Intel LynxPoint southbridge"
#endif
-static void set_var_mtrr(
- unsigned reg, unsigned base, unsigned size, unsigned type)
+static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
+ unsigned int type)
{
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c
index 743b9002cc..ba2538702e 100644
--- a/src/cpu/intel/haswell/finalize.c
+++ b/src/cpu/intel/haswell/finalize.c
@@ -26,7 +26,7 @@
* Revision 1.6.0, June 2012 */
#if 0
-static void msr_set_bit(unsigned reg, unsigned bit)
+static void msr_set_bit(unsigned int reg, unsigned int bit)
{
msr_t msr = rdmsr(reg);
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index ba6d83b785..89869e4418 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -414,8 +414,8 @@ void set_power_limits(u8 power_limit_1_time)
{
msr_t msr = rdmsr(MSR_PLATFORM_INFO);
msr_t limit;
- unsigned power_unit;
- unsigned tdp, min_power, max_power, max_time;
+ unsigned int power_unit;
+ unsigned int tdp, min_power, max_power, max_time;
u8 power_limit_1_val;
if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index 9d2160f754..640d9b37f5 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -53,7 +53,7 @@ int intel_ht_sibling(void)
void intel_sibling_init(struct device *cpu)
{
- unsigned i, siblings;
+ unsigned int i, siblings;
struct cpuid_result result;
/* On the bootstrap processor see if I want sibling cpus enabled */
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c
index 675e6bd9cc..a57f166d48 100644
--- a/src/cpu/intel/model_2065x/bootblock.c
+++ b/src/cpu/intel/model_2065x/bootblock.c
@@ -30,8 +30,8 @@
#error "CPU must be paired with Intel Ibex Peak southbridge"
#endif
-static void set_var_mtrr(
- unsigned reg, unsigned base, unsigned size, unsigned type)
+static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
+ unsigned int type)
{
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c
index 6a729b224c..50e00bf74a 100644
--- a/src/cpu/intel/model_2065x/finalize.c
+++ b/src/cpu/intel/model_2065x/finalize.c
@@ -26,7 +26,7 @@
* Document Number 504790
* Revision 1.6.0, June 2012 */
-static void msr_set_bit(unsigned reg, unsigned bit)
+static void msr_set_bit(unsigned int reg, unsigned int bit)
{
msr_t msr = rdmsr(reg);
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index 68e86a6663..fe095c409d 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -115,7 +115,7 @@ int cpu_get_apic_id_map(int *apic_id_map)
{
int i;
struct cpuid_result result;
- unsigned threads_per_package, threads_per_core;
+ unsigned int threads_per_package, threads_per_core;
/* Logical processors (threads) per core */
result = cpuid_ext(0xb, 0);
@@ -258,7 +258,7 @@ static void configure_mca(void)
static void intel_cores_init(struct device *cpu)
{
struct cpuid_result result;
- unsigned threads_per_package, threads_per_core, i;
+ unsigned int threads_per_package, threads_per_core, i;
/* Logical processors (threads) per core */
result = cpuid_ext(0xb, 0);
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index eaa1870d7a..493d08932c 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -31,8 +31,8 @@
#error "CPU must be paired with Intel BD82X6X or C216 southbridge"
#endif
-static void set_var_mtrr(
- unsigned reg, unsigned base, unsigned size, unsigned type)
+static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
+ unsigned int type)
{
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c
index 870750cc9b..50f49772d4 100644
--- a/src/cpu/intel/model_206ax/finalize.c
+++ b/src/cpu/intel/model_206ax/finalize.c
@@ -26,7 +26,7 @@
* Document Number 504790
* Revision 1.6.0, June 2012 */
-static void msr_set_bit(unsigned reg, unsigned bit)
+static void msr_set_bit(unsigned int reg, unsigned int bit)
{
msr_t msr = rdmsr(reg);
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 600d243cd3..2722454778 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -190,8 +190,8 @@ void set_power_limits(u8 power_limit_1_time)
{
msr_t msr = rdmsr(MSR_PLATFORM_INFO);
msr_t limit;
- unsigned power_unit;
- unsigned tdp, min_power, max_power, max_time;
+ unsigned int power_unit;
+ unsigned int tdp, min_power, max_power, max_time;
u8 power_limit_1_val;
if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
@@ -424,7 +424,7 @@ static void configure_mca(void)
int cpu_get_apic_id_map(int *apic_id_map)
{
struct cpuid_result result;
- unsigned threads_per_package, threads_per_core, i, shift = 0;
+ unsigned int threads_per_package, threads_per_core, i, shift = 0;
/* Logical processors (threads) per core */
result = cpuid_ext(0xb, 0);
@@ -449,7 +449,7 @@ int cpu_get_apic_id_map(int *apic_id_map)
static void intel_cores_init(struct device *cpu)
{
struct cpuid_result result;
- unsigned threads_per_package, threads_per_core, i;
+ unsigned int threads_per_package, threads_per_core, i;
/* Logical processors (threads) per core */
result = cpuid_ext(0xb, 0);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 05:15:37 +0000