diff options
| -rw-r--r-- | src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c | 2 | ||||
| -rw-r--r-- | src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c b/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c index 53fdb16873..e98e5c2fe0 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c +++ b/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c @@ -118,7 +118,7 @@ static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 ra LP4_MRS(p, 1, MR1 , rank); LP4_MRS(p, 2, MR2 , rank); //reverse the DBI - MR3 = ((!tr->DBI_WR & 1)<<7) | ((!tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0); + MR3 = (((!tr->DBI_WR) & 1)<<7) | (((!tr->DBI_RD) & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0); LP4_MRS(p, 3, MR3 , rank); LP4_MRS(p, 11, MR11 , rank); LP4_MRS(p, 12, MR12 , rank); diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c index c228c2cf9f..4a98d8d3c1 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c @@ -987,7 +987,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) DramcTxWindowPerbitCal(p, TX_DQ_DQS_MOVE_DQ_ONLY, FALSE, AUTOK_OFF); #if TX_K_DQM_WITH_WDBI - if ((p->DBI_W_onoff[p->dram_fsp]==DBI_ON)) + if (p->DBI_W_onoff[p->dram_fsp]==DBI_ON) { // K DQM with DBI_ON, and check DQM window spec. //msg("[TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.\n\n"); |