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-rw-r--r--src/include/cpu/amd/gx2def.h31
-rw-r--r--src/mainboard/amd/rumba/auto.c71
-rw-r--r--src/northbridge/amd/gx2/raminit.c2
-rw-r--r--src/southbridge/amd/cs5535/cs5535_early_smbus.c44
-rw-r--r--src/southbridge/amd/cs5535/cs5535_smbus.h90
5 files changed, 115 insertions, 123 deletions
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index e69de29bb2..8f5a6d6dc9 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -0,0 +1,31 @@
+#ifndef CPU_AMD_GX2DEF_H
+#define CPU_AMD_GX2DEF_H
+
+/* GeodeLink Control Processor Registers, GLIU1, Port 3 */
+#define GLCP_CLK_DIS_DELAY 0x4c000008
+#define GLCP_PMCLKDISABLE 0x4c000009
+#define GLCP_DELAY_CONTROLS 0x4c00000f
+#define GLCP_SYS_RSTPLL 0x4c000014
+#define GLCP_DOTPLL 0x4c000015
+
+
+ /* Upper 32 bits */
+#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9
+#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6
+#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0
+
+ /* Lower 32 bits */
+#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
+#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
+
+#define GLCP_SYS_RSTPLL_LOCKWAIT 24
+#define GLCP_SYS_RSTPLL_HOLDCOUNT 16
+#define GLCP_SYS_RSTPLL_BYPASS 15
+#define GLCP_SYS_RSTPLL_PD 14
+#define GLCP_SYS_RSTPLL_RESETPLL 13
+#define GLCP_SYS_RSTPLL_DDRMODE 10
+#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9
+#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8
+#define GLCP_SYS_RSTPLL_CHIP_RESET 0
+
+#endif /* CPU_AMD_GX2DEF_H */
diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index 9163374cff..6b3586b205 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -9,48 +9,32 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
-#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
+#include <cpu/amd/gx2def.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void dump_msr(void)
-{
- int i = 0;
- msr_t msr;
-
- static const unsigned int msrs[] = { 0x20000018, 0x20000019, 0x0};
-
- while (msrs[i] != 0) {
- msr = rdmsr(msrs[i]);
- print_debug("MSR ");
- print_debug_hex32(msrs[i]);
- print_debug("=> ");
- print_debug_hex32(msr.hi);
- print_debug(":");
- print_debug_hex32(msr.lo);
- print_debug("\n\r");
- i++;
- }
-}
-//#include "lib/delay.c"
+#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
+#include "southbridge/amd/cs5535/cs5535_early_setup.c"
#include "northbridge/amd/gx2/raminit.h"
#include "northbridge/amd/gx2/raminit.c"
#include "sdram/generic_sdram.c"
+#include "northbridge/amd/gx2/pll_reset.c"
static void msr_init(void)
{
-
__builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
+
__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
__builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
__builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
__builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
__builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
__builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
+
__builtin_wrmsr(0x10000080, 0x3, 0x0);
__builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
@@ -60,47 +44,12 @@ static void msr_init(void)
__builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
__builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
- __builtin_wrmsr(0x400000e3, 0xf0309c10, 0x0);
- __builtin_wrmsr(0xc0002001, 0x86002, 0x0);
- __builtin_wrmsr(0x80002001, 0x86002, 0x0);
- __builtin_wrmsr(0xa0002001, 0x86002, 0x0);
__builtin_wrmsr(0x50002001, 0x27, 0x0);
__builtin_wrmsr(0x4c002001, 0x1, 0x0);
}
-static void pll_reset(void)
-{
- msr_t msr;
-
- msr = rdmsr(0x4c000014);
- print_debug("CGLP_SYS_RSTPLL ");
- print_debug_hex32(msr.hi);
- print_debug(":");
- print_debug_hex32(msr.lo);
- print_debug("\n\r");
-
- if ((msr.lo >> 26) & 0x3F) {
- print_debug("reboot from BIOS reset\n\r");
- return;
- }
- print_debug("prgramming PLL\n\r");
-
- msr.hi = 0x00000019;
- msr.lo = 0x06de0378;
- wrmsr(0x4c000014, msr);
- msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24));
- wrmsr(0x4c000014, msr);
-
- print_debug("Reset PLL\n\r");
- msr.lo |= ((1<<14) |(1<<13) | (1<<0));
- wrmsr(0x4c000014,msr);
-
- print_debug("should not be here\n\r");
-
-
-}
static void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
@@ -108,15 +57,15 @@ static void main(unsigned long bist)
};
msr_init();
-
+
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
- pll_reset();
-
- msr_init();
+ cs5535_early_setup();
+ pll_reset();
+ //msr_init();
/* Halt if there was a built in self test failure */
//report_bist_failure(bist);
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index e0b5d0e75e..67f5930496 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -102,7 +102,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* load RDSYNC */
msr = rdmsr(0x2000001f);
- msr.hi = 0x000ff300;
+ msr.hi = 0x000ff310;
msr.lo = 0x00000000;
wrmsr(0x2000001f, msr);
diff --git a/src/southbridge/amd/cs5535/cs5535_early_smbus.c b/src/southbridge/amd/cs5535/cs5535_early_smbus.c
index 4a57dd7438..b7dd436887 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_smbus.c
+++ b/src/southbridge/amd/cs5535/cs5535_early_smbus.c
@@ -3,35 +3,39 @@
#define SMBUS_IO_BASE 0x6000
/* initialization for SMBus Controller */
-static int enable_smbus(void)
+static int cs5535_enable_smbus(void)
{
unsigned char val;
- /* FixME: move to early_iobase.c */
- /* setup LBAR for SMBus controller */
- __builtin_wrmsr(0x5140000B, 0x00006000, 0x0000f001);
- /* setup LBAR for GPIO at 0x6100 */
- __builtin_wrmsr(0x5140000C, 0x00006100, 0x0000f001);
-
-
- /* setup GPIO pins for SDA/SCL */
-
- /* Setup SMBus host controller address to 0xEF */
- val = inb(SMBUS_IO_BASE + SMB_ADD);
- val |= (0xEF | SMB_ADD_SAEN);
- outb(val, SMBUS_IO_BASE + SMB_ADD);
+ outb(0, SMBUS_IO_BASE + SMB_CTRL2);
/* Set SCL freq and enable SMB controller */
- outb(0x00, SMBUS_IO_BASE + SMB_CTRL2);
val = inb(SMBUS_IO_BASE + SMB_CTRL2);
- val |= (0x7F < 1) | SMB_CTRL2_ENABLE;
+ val |= ((0x7F << 1) | SMB_CTRL2_ENABLE);
outb(val, SMBUS_IO_BASE + SMB_CTRL2);
- /* Is SDA pulled high ? */
- val = inb(SMBUS_IO_BASE + SMB_CTRL_STS);
- if (val & SMB_CSTS_TSDA)
- return SMBUS_ERROR;
+ /* Setup SMBus host controller address to 0xEF */
+ val = inb(SMBUS_IO_BASE + SMB_ADD);
+ val |= (0xEF | SMB_ADD_SAEN);
+ outb(val, SMBUS_IO_BASE + SMB_ADD);
+#if 0
+ print_debug("SMBUS registers ");
+ print_debug_hex8(inb(SMBUS_IO_BASE));
+ print_debug(" ");
+ print_debug_hex8(inb(SMBUS_IO_BASE + 1));
+ print_debug(" ");
+ print_debug_hex8(inb(SMBUS_IO_BASE + 2));
+ print_debug(" ");
+ print_debug_hex8(inb(SMBUS_IO_BASE + 3));
+ print_debug(" ");
+ print_debug_hex8(inb(SMBUS_IO_BASE + 4));
+ print_debug(" ");
+ print_debug_hex8(inb(SMBUS_IO_BASE + 5));
+ print_debug(" ");
+ print_debug_hex8(inb(SMBUS_IO_BASE + 6));
+ print_debug("\n\r");
+#endif
}
#if 0
diff --git a/src/southbridge/amd/cs5535/cs5535_smbus.h b/src/southbridge/amd/cs5535/cs5535_smbus.h
index 3a2e4928bf..2504f5dbef 100644
--- a/src/southbridge/amd/cs5535/cs5535_smbus.h
+++ b/src/southbridge/amd/cs5535/cs5535_smbus.h
@@ -3,46 +3,49 @@
#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3
-enum smb_native_registers {
- SMB_SDA = 0x00, SMB_STS = 0x01, SMB_CTRL_STS = 0x02,
- SMB_CTRL1 = 0x03, SMB_ADD = 0x04, SMB_CTRL2 = 0x05,
- SMB_CTRL3 = 0x06
-};
-
-enum smb_sts_bits {
- SMB_STS_SLVSTP = (0x01 << 7), SMB_STS_SDAST = (0x01 << 6),
- SMB_STS_BER = (0x01 << 5), SMB_STS_NEGACK = (0x01 << 4),
- SMB_STS_STASTR = (0x01 << 3), SMB_STS_NMATCH = (0x01 << 2),
- SMB_STS_MASTER = (0x01 << 1), SMB_STS_XMIT = (0x01 << 0)
-};
-
-enum smb_ctrl_sts_bits {
- SMB_CSTS_TGSCL = (0x01 << 5), SMB_CSTS_TSDA = (0x01 << 4),
- SMB_CSTS_GCMTCH = (0x01 << 3), SMB_CSTS_MATCH = (0x01 << 2),
- SMB_CSTS_BB = (0x01 << 1), SMB_CSTS_BUSY = (0x01 << 0)
-};
-
-enum smb_ctrl1_bits {
- SMB_CTRL1_STASTRE = (0x01 << 7), SMB_CTRL1_NMINTE = (0x01 << 6),
- SMB_CTRL1_GCMEN = (0x01 << 5), SMB_CTRL1_ACK = (0x01 << 4),
- SMB_CTRL1_RSVD = (0x01 << 3), SMB_CTRL1_INTEN = (0x01 << 2),
- SMB_CTRL1_STOP = (0x01 << 1), SMB_CTRL1_START = (0x01 << 0)
-};
-
-enum smb_add_bits {
- SMB_ADD_SAEN = (0x01 << 7)
-};
-
-enum smb_ctrl2_bits {
- SMB_CTRL2_ENABLE = 0x01,
-};
+#define SMB_SDA 0x00
+#define SMB_STS 0x01
+#define SMB_CTRL_STS 0x02
+#define SMB_CTRL1 0x03
+#define SMB_ADD 0x04
+#define SMB_CTRL2 0x05
+#define SMB_CTRL3 0x06
+
+#define SMB_STS_SLVSTP (0x01 << 7)
+#define SMB_STS_SDAST (0x01 << 6)
+#define SMB_STS_BER (0x01 << 5)
+#define SMB_STS_NEGACK (0x01 << 4)
+#define SMB_STS_STASTR (0x01 << 3)
+#define SMB_STS_NMATCH (0x01 << 2)
+#define SMB_STS_MASTER (0x01 << 1)
+#define SMB_STS_XMIT (0x01 << 0)
+
+#define SMB_CSTS_TGSCL (0x01 << 5)
+#define SMB_CSTS_TSDA (0x01 << 4)
+#define SMB_CSTS_GCMTCH (0x01 << 3)
+#define SMB_CSTS_MATCH (0x01 << 2)
+#define SMB_CSTS_BB (0x01 << 1)
+#define SMB_CSTS_BUSY (0x01 << 0)
+
+#define SMB_CTRL1_STASTRE (0x01 << 7)
+#define SMB_CTRL1_NMINTE (0x01 << 6)
+#define SMB_CTRL1_GCMEN (0x01 << 5)
+#define SMB_CTRL1_ACK (0x01 << 4)
+#define SMB_CTRL1_RSVD (0x01 << 3)
+#define SMB_CTRL1_INTEN (0x01 << 2)
+#define SMB_CTRL1_STOP (0x01 << 1)
+#define SMB_CTRL1_START (0x01 << 0)
+
+#define SMB_ADD_SAEN (0x01 << 7)
+
+#define SMB_CTRL2_ENABLE 0x01
#define SMBUS_TIMEOUT (100*1000*10)
#define SMBUS_STATUS_MASK 0xfbff
-static inline void smbus_delay(void)
+static void smbus_delay(void)
{
- outb(0x80, 0x80);
+ outb(0x80, 0x80);
}
/* generate a smbus start condition */
@@ -124,19 +127,24 @@ static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
-static int do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
+static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
{
unsigned char val;
- smbus_start_condition(smbus_io_base);
+ if (smbus_start_condition(smbus_io_base) < 0)
+ print_debug("smbus error 1");
- smbus_send_slave_address(smbus_io_base, device);
+ if (smbus_send_slave_address(smbus_io_base, device) < 0)
+ print_debug("smbus error 2");
- smbus_send_command(smbus_io_base, address);
+ if (smbus_send_command(smbus_io_base, address) < 0)
+ print_debug("smbus error 3");
- smbus_start_condition(smbus_io_base);
+ if (smbus_start_condition(smbus_io_base) < 0)
+ print_debug("smbus error 4");
- smbus_send_slave_address(smbus_io_base, device | 0x01);
+ if (smbus_send_slave_address(smbus_io_base, device | 0x01))
+ print_debug("smbus error 5");
val = inb(smbus_io_base + SMB_CTRL1);
outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 20:28:49 +0000