diff options
| -rw-r--r-- | src/mainboard/google/brya/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/kano/gpio.c | 4 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/kano/overridetree.cb | 16 |
3 files changed, 21 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 94a1428fea..850a78c1f5 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -14,6 +14,7 @@ config BOARD_GOOGLE_BRYA_COMMON def_bool y select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_ALC1015 + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index aaac0ca03e..818ddd06ae 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -30,10 +30,14 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_D3, NONE), /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> APU_PEN_DETECT_ODL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_D6, NONE, PLTRST), /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), /* D8 : SRCCLKREQ3# ==> NC */ PAD_NC(GPP_D8, NONE), + /* D17 : UART1_RXD ==> APU_PEN_DETECT_ODL */ + PAD_CFG_GPI_SCI(GPP_D17, NONE, DEEP, EDGE_SINGLE, NONE), /* D18 : UART1_TXD ==> NC */ PAD_NC(GPP_D18, NONE), diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 899dd36f6f..f2b04db46d 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -15,6 +15,9 @@ end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" + # GPE configuration + register "pmc_gpe0_dw1" = "GPP_D" + # FIVR configurations for kano are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. register "ext_fivr_settings" = "{ @@ -223,6 +226,19 @@ chip soc/intel/alderlake register "hid_desc_reg_offset" = "0x01" device i2c 0x10 on end end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + # GPP_D6 is the IRQ source, and GPP_D17 is the wake source + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D6)" + register "key.wake_gpe" = "GPE0_DW1_17" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end end device ref i2c2 on chip drivers/i2c/sx9324 |