diff options
| -rw-r--r-- | src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 10 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/chip.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/espi.c | 17 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/pmc.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/pmc.c | 31 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/systemagent.c | 11 |
9 files changed, 42 insertions, 46 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 7350319b22..8d847f73fc 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -305,7 +305,7 @@ chip soc/intel/tigerlake end end # eSPI device pci 1f.1 off end # P2SB - device pci 1f.2 on end # PMC + device pci 1f.2 hidden end # PMC device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI Flash Controller diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index fa99de8c8f..5d5dcc4b70 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -370,7 +370,7 @@ chip soc/intel/tigerlake register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" device spi 0 on end end - end # GSPI0 0xA0AA + end # GSPI0 0xA0AA device pci 1e.3 on chip drivers/spi/acpi register "name" = ""CRFP"" @@ -380,14 +380,14 @@ chip soc/intel/tigerlake register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" device spi 0 on end end # FPMCU - end # GSPI1 0xA0AB + end # GSPI1 0xA0AB device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end end - end # eSPI 0xA080 - A09F + end # eSPI 0xA080 - A09F device pci 1f.1 off end # P2SB 0xA0A0 - device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.2 hidden end # PMC 0xA0A1 device pci 1f.3 on chip drivers/generic/max98357a register "hid" = ""MX98357A"" @@ -395,7 +395,7 @@ chip soc/intel/tigerlake register "sdmode_delay" = "5" device generic 0 on end end - end # Intel HD audio 0xA0C8-A0CF + end # Intel HD audio 0xA0C8-A0CF device pci 1f.4 off end # SMBus 0xA0A3 device pci 1f.5 on end # SPI 0xA0A4 device pci 1f.6 off end # GbE 0x15E1/0x15E2 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 82f358e8b6..045dc89e4d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -243,7 +243,7 @@ chip soc/intel/tigerlake device pci 1e.3 off end # GSPI1 0xA0AB device pci 1f.0 on end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 - device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.2 hidden end # PMC 0xA0A1 device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF device pci 1f.4 on end # SMBus 0xA0A3 device pci 1f.5 on end # SPI 0xA0A4 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index fec2fefa16..83b6c0ae0c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -239,7 +239,7 @@ chip soc/intel/tigerlake device pci 1e.3 off end # GSPI1 0xA0AB device pci 1f.0 on end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 - device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.2 hidden end # PMC 0xA0A1 device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF device pci 1f.4 on end # SMBus 0xA0A3 device pci 1f.5 on end # SPI 0xA0A4 diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index c1764cde93..a923074acc 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> @@ -151,11 +152,17 @@ static struct device_operations cpu_bus_ops = { static void soc_enable(struct device *dev) { - /* Set the operations if it is a special bus type */ + /* + * Set the operations if it is a special bus type or a hidden PCI + * device. + */ if (dev->path.type == DEVICE_PATH_DOMAIN) dev->ops = &pci_domain_ops; else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &cpu_bus_ops; + else if (dev->path.type == DEVICE_PATH_PCI && + dev->path.pci.devfn == PCH_DEVFN_PMC) + dev->ops = &pmc_ops; } struct chip_operations soc_intel_tigerlake_ops = { diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index ed8481a389..8cc83036d5 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -197,21 +197,4 @@ void lpc_soc_init(struct device *dev) soc_mirror_dmi_pcr_io_dec(); } -/* Fill up ESPI IO resource structure inside SoC directory */ -void pch_lpc_soc_fill_io_resources(struct device *dev) -{ - /* - * PMC pci device gets hidden from PCI bus due to Silicon - * policy hence bind ACPI BASE aka ABASE (offset 0x20) with - * ESPI IO resources to ensure that ABASE falls under PCI reserved - * IO memory range. - * - * Note: Don't add any more resource with same offset 0x20 - * under this device space. - */ - pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4, - ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED); -} - #endif diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index 3b58a74b6d..0f72833fbe 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -3,6 +3,10 @@ #ifndef _SOC_TIGERLAKE_PMC_H_ #define _SOC_TIGERLAKE_PMC_H_ +#include <device/device.h> + +extern struct device_operations pmc_ops; + /* PCI Configuration Space (D31:F2): PMC */ #define PWRMBASE 0x10 #define ABASE 0x20 diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 136f1030a3..fa59d467e2 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -75,7 +75,7 @@ static void config_deep_sx(uint32_t deepsx_config) write32(pmcbase + DSX_CFG, reg); } -static void pmc_init(void *unused) +static void pmc_init(struct device *dev) { const config_t *config = config_of_soc(); @@ -91,11 +91,24 @@ static void pmc_init(void *unused) config_deep_sx(config->deep_sx_config); } -/* -* Initialize PMC controller. -* -* PMC controller gets hidden from PCI bus during FSP-Silicon init call. -* Hence PCI enumeration can't be used to initialize bus device and -* allocate resources. -*/ -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL); +static void soc_pmc_read_resources(struct device *dev) +{ + struct resource *res; + + /* Add the fixed MMIO resource */ + mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + + /* Add the fixed I/O resource */ + res = new_resource(dev, 1); + res->base = (resource_t)ACPI_BASE_ADDRESS; + res->size = (resource_t)ACPI_BASE_SIZE; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +struct device_operations pmc_ops = { + .read_resources = soc_pmc_read_resources, + .set_resources = noop_set_resources, + .enable = pmc_init, + .scan_bus = scan_static_bus, +}; diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 977c6674e7..8c0a42a71a 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -32,17 +32,6 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, - /* - * PMC pci device gets hidden from PCI bus due to Silicon - * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with - * SA resources to ensure that PMCBAR falls under PCI reserved - * memory range. - * - * Note: Don't add any more resource with same offset 0x10 - * under this device space. - */ - { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, - "PMCBAR" }, }; sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, |