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-rw-r--r--src/mainboard/intel/eagleheights/romstage.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 13c7e951f3..71bda84c0f 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -163,7 +163,7 @@ void early_config(void) {
pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
}
-void real_main(unsigned long bist)
+void main(unsigned long bist)
{
/* int boot_mode = 0; */
@@ -232,6 +232,3 @@ void real_main(unsigned long bist)
sdram_initialize(ARRAY_SIZE(mch), mch);
}
-/* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */
-#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
-