diff options
3 files changed, 18 insertions, 18 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 0b3568b646..df13fef43c 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -93,12 +93,6 @@ chip soc/intel/tigerlake register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)" register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # NVMe PCIE 9 using clk 0 register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" @@ -508,6 +502,12 @@ chip soc/intel/tigerlake end # FPMCU end device ref pch_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec device pnp 0c09.0 on end end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 1bce4b20a8..af16f756f0 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -17,12 +17,6 @@ chip soc/intel/tigerlake # CPU replacement check register "CpuReplacementCheck" = "1" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - register "PcieRpSlotImplemented[2]" = "1" register "PcieRpSlotImplemented[3]" = "1" register "PcieRpSlotImplemented[8]" = "1" @@ -303,6 +297,12 @@ chip soc/intel/tigerlake end end device ref pch_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 7a310988a8..3a80c51d9b 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -17,12 +17,6 @@ chip soc/intel/tigerlake # CPU replacement check register "CpuReplacementCheck" = "1" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - register "PcieRpSlotImplemented[2]" = "1" register "PcieRpSlotImplemented[3]" = "1" register "PcieRpSlotImplemented[8]" = "1" @@ -308,6 +302,12 @@ chip soc/intel/tigerlake end end device ref pch_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] |