diff options
3 files changed, 133 insertions, 15 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 8722d718d8..8a5c97e46a 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -97,42 +97,47 @@ chip soc/intel/alderlake .i2c[0] = { .early_init = 1, .speed = I2C_SPEED_FAST, - .data_hold_time_ns = 50, .speed_config[0] = { - .scl_lcnt = 157, - .scl_hcnt = 78, + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, } }, .i2c[1] = { .speed = I2C_SPEED_FAST, - .data_hold_time_ns = 50, .speed_config[0] = { - .scl_lcnt = 157, - .scl_hcnt = 78, + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, } }, .i2c[2] = { .speed = I2C_SPEED_FAST, - .data_hold_time_ns = 50, .speed_config[0] = { - .scl_lcnt = 157, - .scl_hcnt = 78, + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, } }, .i2c[3] = { .speed = I2C_SPEED_FAST, - .data_hold_time_ns = 50, .speed_config[0] = { - .scl_lcnt = 157, - .scl_hcnt = 78, + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, } }, .i2c[5] = { .speed = I2C_SPEED_FAST, - .data_hold_time_ns = 50, .speed_config[0] = { - .scl_lcnt = 157, - .scl_hcnt = 78, + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, } }, }" diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb index c377e5b83c..0ea78ea76e 100644 --- a/src/mainboard/google/brya/variants/nereid/overridetree.cb +++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb @@ -34,6 +34,58 @@ chip soc/intel/alderlake .vnn_icc_max_ma = 500, }" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | Sub-board(PSensor)/WCAM | + #| I2C3 | Audio | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 160, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 152, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index 34b142a0eb..267cf45c20 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -50,6 +50,67 @@ chip soc/intel/alderlake .vnn_icc_max_ma = 500, }" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | Sub-board(PSensor)/WCAM | + #| I2C3 | Audio | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 160, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf |