diff options
| -rw-r--r-- | src/mainboard/google/deltaur/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 332 |
2 files changed, 333 insertions, 0 deletions
diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index dcbe5ecbad..6b4af9b592 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -4,6 +4,7 @@ config BOARD_GOOGLE_BASEBOARD_DELTAUR select DRIVERS_I2C_GENERIC select DRIVERS_INTEL_ISH select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI select EC_GOOGLE_WILCO select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index a4031622ef..a63d66c834 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -3,4 +3,336 @@ chip soc/intel/tigerlake device cpu_cluster 0 on device lapic 0 on end end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + + # TODO: Figure out GPE DW1&2 + register "pmc_gpe0_dw0" = "GPP_C" + #register "pmc_gpe0_dw1" = "??" + #register "pmc_gpe0_dw2" = "??" + + # Wilco EC host command ranges + register "gen1_dec" = "0x00040931" # 0x930-0x937 + register "gen2_dec" = "0x00040941" # 0x940-0x947 + register "gen3_dec" = "0x000c0951" # 0x950-0x95f + + register "s0ix_enable" = "1" + + # TODO: not yet + register "dptf_enable" = "0" + + register "tcc_offset" = "0" + + # FSP configuration + register "SaGv" = "SaGv_Disabled" + + register "SataEnable" = "1" + register "SataMode" = "0" + register "SataSalpSupport" = "1" + register "SmbusEnable" = "1" + + # TODO: the lengths are all MID for right now. + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # Ext USB Port 1 (Right) + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Ext USB Port 2 (Left) + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # M.2 3042 (WWAN) + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB Port 2 + + # PCIe root port 6 (WLAN), clock 1 + register "PcieRpEnable[5]" = "1" + register "PcieClkSrcUsage[1]" = "5" + register "PcieClkSrcClkReq[1]" = "1" + + # PCIe root port 7 (Card Reader), clock 4 + register "PcieRpEnable[6]" = "1" + register "PcieClkSrcUsage[4]" = "6" + register "PcieClkSrcClkReq[4]" = "4" + + # PCIe port root 8 (LAN), clock 3 + register "PcieRpEnable[7]" = "1" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" + register "PcieClkSrcClkReq[3]" = "3" + + # PCIe root port 9 (NVMe), clock 2 + register "PcieRpEnable[8]" = "1" + register "PcieClkSrcUsage[2]" = "8" + register "PcieClkSrcClkReq[2]" = "2" + + # Mark unused SRCCLKREQs as so + register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| I2C0 | Touchscreen | + #| I2C1 | Touchpad | + #| I2C2 | ISH ? | + #| I2C3 | cr50 TPM | + #| I2C5 | ISH ? | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .early_init = 1, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[0]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "1" + + # TCSS USB3 + register "TcssXhciEn" = "1" + + # DisplayPort + register "DdiPortAConfig" = "1" # eDP + register "DdiPortAHpd" = "1" + + # Disable PM to allow for shorter irq pulses + register "gpio_override_pm" = "1" + register "gpio_pm[0]" = "0" + register "gpio_pm[1]" = "0" + register "gpio_pm[2]" = "0" + register "gpio_pm[3]" = "0" + register "gpio_pm[4]" = "0" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF + device pci 05.0 off end # IPU + device pci 06.0 off end # PEG60 + device pci 07.0 on end # TBT_PCIe0 + device pci 07.1 on end # TBT_PCIe0 + device pci 07.2 on end # TBT_PCIe0 + device pci 07.3 on end # TBT_PCIe0 + device pci 08.0 on end # GNA + device pci 09.0 off end # NPK + device pci 0a.0 off end # Crash-log SRAM + device pci 0d.0 on end # USB xHCI + device pci 0d.1 off end # USB xDCI + device pci 0d.2 off end # TBT DMA0 + device pci 0d.3 off end # TBT DMA1 + device pci 0e.0 off end # VMD + + device pci 10.0 off end # THC #0 + device pci 10.1 off end # THC #1 + device pci 10.2 on end # CNVi Bluetooth + device pci 11.0 off end # UART #3 + device pci 11.1 off end # UART4 + device pci 11.2 off end # UART5 + device pci 11.3 off end # UART6 + + device pci 12.0 on end # ISH + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # GSPI #3 + device pci 13.1 off end # GSPI #4 + device pci 13.2 off end # GSPI #5 + device pci 13.3 off end # GSPI #6 + + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 1 (Right)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 2 (Left)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""M.2 3042 (WWAN)"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USH"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""M.2 2230 (BT)"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 1 (Right)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 2 (Left)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.4 on end + end + end + end + end # USB 3.2 2x1 xHCI HC + + device pci 14.1 off end # USB 3.2 1x1 xDCI HC + device pci 14.2 on end # Shared SRAM + + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi WiFi + end + + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + device i2c 50 on end + end + end # I2C #3 + + device pci 16.0 on end # HECI #1 + device pci 16.1 off end # HECI #2 + device pci 16.2 off end # IDE-R + device pci 16.3 off end # KT-T + device pci 16.4 on end # HECI #3 + device pci 16.5 on end # HECI #4 + device pci 17.0 on end # SATA (AHCI) + device pci 19.0 off end # I2C #4 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # UART #2 + + device pci 1c.0 on end # PCIe Root Port #1 (USB) + device pci 1c.1 on end # PCIe Root Port #2 (USB) + device pci 1c.2 off end # PCIe Root Port #3 () + device pci 1c.3 on end # PCIe Root Port #4 (WWAN) + device pci 1c.4 on end # PCIe Root Port #5 (LTE) + device pci 1c.5 on end # PCIe Root Port #6 (WiFi) + device pci 1c.6 on end # PCIe Root Port #7 (Card reader) + device pci 1c.7 on + chip drivers/net + register "wake" = "GPE0_PME_B0" + device pci 00.0 on end + end + end # PCIe Root Port #8 (LAN) + device pci 1d.0 on end # PCIe Root Port #9 (NVMe) + device pci 1d.1 off end # PCIe Root Port #10 (NVMe) + device pci 1d.2 off end # PCIe Root Port #11 (NVMe) + device pci 1d.3 off end # PCIe Root Port #12 (NVMe) + + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + + device pci 1f.0 on + chip ec/google/wilco + device pnp 0c09.0 on end + end + end # eSPI + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # PMC + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI Flash Controller + device pci 1f.6 on end # GbE Controller + device pci 1f.7 off end # Intel Trace Hub + end end |