diff options
| -rw-r--r-- | src/mainboard/google/guybrush/bootblock.c | 24 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/espi_util.c | 33 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/espi.h | 4 |
4 files changed, 41 insertions, 21 deletions
diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 2791a8ff6f..800e70a294 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -1,15 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/acpimmio.h> #include <amdblocks/espi.h> -#include <amdblocks/lpc.h> #include <bootblock_common.h> #include <baseboard/variants.h> #include <console/console.h> #include <delay.h> -#include <device/pci_ops.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> +#include <soc/espi.h> #include <soc/southbridge.h> #include <timer.h> @@ -30,16 +26,10 @@ void mb_set_up_early_espi(void) void bootblock_mainboard_early_init(void) { - uint32_t dword; size_t num_gpios, override_num_gpios; const struct soc_amd_gpio *gpios, *override_gpios; - /* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped - on Picasso and older compared to Renoir/Cezanne and newer */ - dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); - dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); - dword |= LPC_LDRQ0_PD_EN; - pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); + espi_disable_lpc_ldrq(); /* * All LPC decodes need to be cleared before we can configure the LPC pads as secondary @@ -67,15 +57,7 @@ void bootblock_mainboard_early_init(void) /* Early eSPI interface configuration */ - /* Use SPI2 pins for eSPI */ - dword = pm_read32(PM_SPI_PAD_PU_PD); - dword |= PM_ESPI_CS_USE_DATA2; - pm_write32(PM_SPI_PAD_PU_PD, dword); - - /* Switch the pads that can be used as either LPC or secondary eSPI to 1.8V mode */ - dword = pm_read32(PM_ACPI_CONF); - dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; - pm_write32(PM_ACPI_CONF, dword); + espi_switch_to_spi2_pads(); } void bootblock_mainboard_init(void) diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 050ba44be9..5fda4b0b82 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -10,6 +10,7 @@ all-y += aoac.c bootblock-y += bootblock.c bootblock-y += early_fch.c +bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c bootblock-y += reset.c diff --git a/src/soc/amd/cezanne/espi_util.c b/src/soc/amd/cezanne/espi_util.c new file mode 100644 index 0000000000..ceb87243e2 --- /dev/null +++ b/src/soc/amd/cezanne/espi_util.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <amdblocks/lpc.h> +#include <device/pci_ops.h> +#include <soc/espi.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/southbridge.h> +#include <types.h> + +void espi_disable_lpc_ldrq(void) +{ + /* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped + on Picasso and older compared to Renoir/Cezanne and newer */ + uint32_t dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); + dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); + dword |= LPC_LDRQ0_PD_EN; + pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); +} + +void espi_switch_to_spi2_pads(void) +{ + /* Use SPI2 pins for eSPI */ + uint32_t dword = pm_read32(PM_SPI_PAD_PU_PD); + dword |= PM_ESPI_CS_USE_DATA2; + pm_write32(PM_SPI_PAD_PU_PD, dword); + + /* Switch the pads that can be used as either LPC or secondary eSPI to 1.8V mode */ + dword = pm_read32(PM_ACPI_CONF); + dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; + pm_write32(PM_ACPI_CONF, dword); +} diff --git a/src/soc/amd/cezanne/include/soc/espi.h b/src/soc/amd/cezanne/include/soc/espi.h new file mode 100644 index 0000000000..9836ef7686 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/espi.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +void espi_disable_lpc_ldrq(void); +void espi_switch_to_spi2_pads(void); |