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-rw-r--r--src/northbridge/intel/sandybridge/raminit.c2
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c44
-rw-r--r--src/northbridge/intel/sandybridge/raminit_iosav.c14
-rw-r--r--src/northbridge/intel/sandybridge/raminit_native.c6
4 files changed, 33 insertions, 33 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 8acfb98b57..1d4354c83d 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -309,7 +309,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
wait_txt_clear();
- wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 });
+ wrmsr(0x2e6, (msr_t) { .lo = 0, .hi = 0 });
const u32 sskpd = MCHBAR32(SSKPD); // !!! = 0x00000000
if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 && sskpd && !s3resume) {
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index ccf240372c..0b8e5ef20f 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -44,7 +44,7 @@ static u32 get_XOVER_CMD(u8 rankmap)
u32 reg;
/* Enable xover cmd */
- reg = 0x4000;
+ reg = 1 << 14;
/* Enable xover ctl */
if (rankmap & 0x03)
@@ -877,7 +877,7 @@ void dram_mrscommands(ramctr_timing *ctrl)
.data_direction = SSQ_NA,
},
.sp_cmd_addr = {
- .address = 1024,
+ .address = 1 << 10,
.rowbits = 6,
.bank = 0,
.rank = 0,
@@ -1145,7 +1145,7 @@ static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int slotrank, i
FOR_ALL_LANES {
ctrl->timings[channel][slotrank].lanes[lane].rcven
- = upperA[lane] + rcven_delta + 0x40;
+ = upperA[lane] + rcven_delta + 64;
}
program_timings(ctrl, channel);
@@ -1234,7 +1234,7 @@ static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank
printram("4028 += 2;\n");
/* Guard against I/O latency overflow */
- if (ctrl->timings[channel][slotrank].io_latency >= 0x10) {
+ if (ctrl->timings[channel][slotrank].io_latency >= 16) {
printk(BIOS_EMERG, "I/O latency overflow: %d, %d\n",
channel, slotrank);
return MAKE_ERR;
@@ -1350,7 +1350,7 @@ int receive_enable_calibration(ramctr_timing *ctrl)
all_high = 1;
some_high = 0;
FOR_ALL_LANES {
- if (ctrl->timings[channel][slotrank].lanes[lane].rcven >= 0x40)
+ if (ctrl->timings[channel][slotrank].lanes[lane].rcven >= 64)
some_high = 1;
else
all_high = 0;
@@ -1360,8 +1360,8 @@ int receive_enable_calibration(ramctr_timing *ctrl)
ctrl->timings[channel][slotrank].io_latency--;
printram("4028--;\n");
FOR_ALL_LANES {
- ctrl->timings[channel][slotrank].lanes[lane].rcven -= 0x40;
- upperA[lane] -= 0x40;
+ ctrl->timings[channel][slotrank].lanes[lane].rcven -= 64;
+ upperA[lane] -= 64;
}
} else if (some_high) {
@@ -1516,7 +1516,7 @@ static void program_wdb_pattern_length(int channel, const unsigned int num_cache
static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b)
{
unsigned int j;
- unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40;
+ unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 64;
for (j = 0; j < 16; j++)
write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a);
@@ -1537,8 +1537,8 @@ static int num_of_channels(const ramctr_timing *ctrl)
static void fill_pattern1(ramctr_timing *ctrl, int channel)
{
unsigned int j;
- unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40;
- unsigned int channel_step = 0x40 * num_of_channels(ctrl);
+ unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 64;
+ unsigned int channel_step = 64 * num_of_channels(ctrl);
for (j = 0; j < 16; j++)
write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff);
@@ -1676,7 +1676,7 @@ static void train_write_flyby(ramctr_timing *ctrl)
.data_direction = SSQ_NA,
},
.sp_cmd_addr = {
- .address = 1024,
+ .address = 1 << 10,
.rowbits = 6,
.bank = 0,
.rank = slotrank,
@@ -1933,8 +1933,8 @@ static int test_command_training(ramctr_timing *ctrl, int channel, int slotrank)
static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno)
{
unsigned int i, j;
- unsigned int offset = get_precedening_channels(ctrl, channel) * 0x40;
- unsigned int step = 0x40 * num_of_channels(ctrl);
+ unsigned int offset = get_precedening_channels(ctrl, channel) * 64;
+ unsigned int step = 64 * num_of_channels(ctrl);
if (patno) {
u8 base8 = 0x80 >> ((patno - 1) % 8);
@@ -2218,8 +2218,8 @@ int read_mpr_training(ramctr_timing *ctrl)
* FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will
* also use a single loop. It would seem that it is a debugging configuration.
*/
- MCHBAR32(IOSAV_DC_MASK) = 0x300;
- printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300);
+ MCHBAR32(IOSAV_DC_MASK) = 3 << 8;
+ printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 3 << 8);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
err = find_read_mpr_margin(ctrl, channel, slotrank,
@@ -2228,8 +2228,8 @@ int read_mpr_training(ramctr_timing *ctrl)
return err;
}
- MCHBAR32(IOSAV_DC_MASK) = 0x200;
- printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200);
+ MCHBAR32(IOSAV_DC_MASK) = 2 << 8;
+ printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 2 << 8);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
err = find_read_mpr_margin(ctrl, channel, slotrank,
@@ -2353,8 +2353,8 @@ int aggressive_read_training(ramctr_timing *ctrl)
* FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will
* also use a single loop. It would seem that it is a debugging configuration.
*/
- MCHBAR32(IOSAV_DC_MASK) = 0x300;
- printram("discover falling edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300);
+ MCHBAR32(IOSAV_DC_MASK) = 3 << 8;
+ printram("discover falling edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 3 << 8);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
err = find_agrsv_read_margin(ctrl, channel, slotrank,
@@ -2363,8 +2363,8 @@ int aggressive_read_training(ramctr_timing *ctrl)
return err;
}
- MCHBAR32(IOSAV_DC_MASK) = 0x200;
- printram("discover rising edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200);
+ MCHBAR32(IOSAV_DC_MASK) = 2 << 8;
+ printram("discover rising edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 2 << 8);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
err = find_agrsv_read_margin(ctrl, channel, slotrank,
@@ -2971,7 +2971,7 @@ void restore_timings(ramctr_timing *ctrl)
MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0;
FOR_ALL_CHANNELS {
- MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000);
+ MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~(0x3f << 24));
udelay(2);
}
}
diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c
index cb49e0ce0e..86b3baaa01 100644
--- a/src/northbridge/intel/sandybridge/raminit_iosav.c
+++ b/src/northbridge/intel/sandybridge/raminit_iosav.c
@@ -94,7 +94,7 @@ void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap)
.data_direction = SSQ_NA,
},
.sp_cmd_addr = {
- .address = 1024,
+ .address = 1 << 10,
.rowbits = 6,
.bank = 0,
.rank = slotrank,
@@ -216,7 +216,7 @@ void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int sl
.data_direction = SSQ_NA,
},
.sp_cmd_addr = {
- .address = 1024,
+ .address = 1 << 10,
.rowbits = 6,
.bank = 0,
.rank = slotrank,
@@ -284,7 +284,7 @@ void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int sl
.data_direction = SSQ_NA,
},
.sp_cmd_addr = {
- .address = 1024,
+ .address = 1 << 10,
.rowbits = 6,
.bank = 0,
.rank = slotrank,
@@ -572,7 +572,7 @@ void iosav_write_command_training_sequence(
.data_direction = SSQ_NA,
},
.sp_cmd_addr = {
- .address = 1024,
+ .address = 1 << 10,
.rowbits = 6,
.bank = 0,
.rank = slotrank,
@@ -670,7 +670,7 @@ void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int slotr
.data_direction = SSQ_NA,
},
.sp_cmd_addr = {
- .address = 1024,
+ .address = 1 << 10,
.rowbits = 6,
.bank = 0,
.rank = slotrank,
@@ -765,7 +765,7 @@ void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel
.data_direction = SSQ_NA,
},
.sp_cmd_addr = {
- .address = 1024,
+ .address = 1 << 10,
.rowbits = 6,
.bank = 0,
.rank = slotrank,
@@ -860,7 +860,7 @@ void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slot
.data_direction = SSQ_NA,
},
.sp_cmd_addr = {
- .address = 1024,
+ .address = 1 << 10,
.rowbits = 6,
.bank = 0,
.rank = slotrank,
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index 3613c050ab..0d581f5a57 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -577,13 +577,13 @@ static void dram_freq(ramctr_timing *ctrl)
/* Step 2 - Select frequency in the MCU */
reg1 = ctrl->FRQ;
if (ctrl->base_freq == 100)
- reg1 |= 0x100; /* Enable 100Mhz REF clock */
+ reg1 |= (1 << 8); /* Enable 100Mhz REF clock */
- reg1 |= 0x80000000; /* set running bit */
+ reg1 |= (1 << 31); /* set running bit */
MCHBAR32(MC_BIOS_REQ) = reg1;
int i = 0;
printk(BIOS_DEBUG, "PLL busy... ");
- while (reg1 & 0x80000000) {
+ while (reg1 & (1 << 31)) {
udelay(10);
i++;
reg1 = MCHBAR32(MC_BIOS_REQ);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 22:04:37 +0000