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-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/devicetree.cb2
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb2
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb2
-rw-r--r--src/soc/amd/cezanne/chip.h3
-rw-r--r--src/soc/amd/picasso/chip.h3
5 files changed, 7 insertions, 5 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index 30ebe62ef4..f9a1201d68 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -58,7 +58,7 @@ chip soc/amd/cezanne
register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR
register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC
- register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
+ register "pspp_policy" = "DXIO_PSPP_BALANCED"
register "usb_phy_custom" = "1"
register "usb_phy" = "{
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index 0cf969cf6a..92ca4e30ed 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -250,7 +250,7 @@ chip soc/amd/picasso
register "gpp_clk_config[5]" = "GPP_CLK_OFF"
register "gpp_clk_config[6]" = "GPP_CLK_OFF"
- register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
+ register "pspp_policy" = "DXIO_PSPP_BALANCED"
# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 637299b43d..8b1c68a367 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -243,7 +243,7 @@ chip soc/amd/picasso
register "gpp_clk_config[5]" = "GPP_CLK_OFF"
register "gpp_clk_config[6]" = "GPP_CLK_OFF"
- register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
+ register "pspp_policy" = "DXIO_PSPP_BALANCED"
# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h
index 319ce4108e..850d1bbbda 100644
--- a/src/soc/amd/cezanne/chip.h
+++ b/src/soc/amd/cezanne/chip.h
@@ -97,7 +97,8 @@ struct soc_amd_cezanne_config {
/* performance policy for the PCIe links: power consumption vs. link speed */
enum {
- DXIO_PSPP_PERFORMANCE = 0,
+ DXIO_PSPP_DISABLED = 0,
+ DXIO_PSPP_PERFORMANCE,
DXIO_PSPP_BALANCED,
DXIO_PSPP_POWERSAVE,
} pspp_policy;
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 4c43b1fdff..63898308e7 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -265,7 +265,8 @@ struct soc_amd_picasso_config {
/* performance policy for the PCIe links: power consumption vs. link speed */
enum {
- DXIO_PSPP_PERFORMANCE = 0,
+ DXIO_PSPP_DISABLED = 0,
+ DXIO_PSPP_PERFORMANCE,
DXIO_PSPP_BALANCED,
DXIO_PSPP_POWERSAVE,
} pspp_policy;