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-rw-r--r--src/soc/nvidia/tegra124/include/soc/clock.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h
index c0a3f398e3..d4c504642b 100644
--- a/src/soc/nvidia/tegra124/include/soc/clock.h
+++ b/src/soc/nvidia/tegra124/include/soc/clock.h
@@ -225,6 +225,17 @@ enum {
#define clock_configure_source(device, src, freq) \
clock_configure_irregular_source(device, src, freq, src)
+/* The I2C divisors are not 7.1 divisors like the others, they divide by n + 1
+ * directly. Also, there are internal divisors in the I2C controller itself.
+ * We can deal with those here and make it easier to select what the actual
+ * bus frequency will be. The 0x19 value is the default divisor in the
+ * clk_divisor register in the controller, and 8 is just a magic number in the
+ * documentation. Multiplying by 2 compensates for the different format of the
+ * divisor.
+ */
+#define clock_configure_i2c_scl_freq(device, src, freq) \
+ clock_configure_source(device, src, (freq) * (0x19 + 1) * 8 * 2)
+
enum clock_source { /* Careful: Not true for all sources, always check TRM! */
PLLP = 0,
PLLC2 = 1,