diff options
| -rw-r--r-- | src/mainboard/google/brya/variants/pujjo/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/pujjo/overridetree.cb | 17 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/pujjo/variant.c | 33 |
3 files changed, 40 insertions, 11 deletions
diff --git a/src/mainboard/google/brya/variants/pujjo/Makefile.inc b/src/mainboard/google/brya/variants/pujjo/Makefile.inc index 8ae0e3b61c..e04a887191 100644 --- a/src/mainboard/google/brya/variants/pujjo/Makefile.inc +++ b/src/mainboard/google/brya/variants/pujjo/Makefile.inc @@ -4,4 +4,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += variant.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb index 552b24472f..16b6a136a6 100644 --- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb @@ -24,6 +24,10 @@ fw_config field AUDIO 12 14 option ALC1019_ALC5682IVS 0 end + field EXT_VR 15 + option EXT_VR_PRESENT 0 + option EXT_VR_ABSENT 1 + end end @@ -55,19 +59,10 @@ chip soc/intel/alderlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN - # Configure external V1P05/Vnn/VnnSx Rails + # FIVR configurations for Pujjoteen are disabled since the board doesn't have V1p05 and Vnn + # bypass rails implemented. register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, - .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, - .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, - .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, - .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, - .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, - .v1p05_voltage_mv = 1050, - .vnn_voltage_mv = 780, - .vnn_sx_voltage_mv = 1050, - .v1p05_icc_max_ma = 500, - .vnn_icc_max_ma = 500, }" # Intel Common SoC Config diff --git a/src/mainboard/google/brya/variants/pujjo/variant.c b/src/mainboard/google/brya/variants/pujjo/variant.c new file mode 100644 index 0000000000..54542f4dcd --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjo/variant.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fw_config.h> +#include <baseboard/variants.h> + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + // Configure external V1P05/Vnn/VnnSx Rails for Pujjo, Pujjoflex + if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_PRESENT))) { + config->ext_fivr_settings.configure_ext_fivr = 1; + + config->ext_fivr_settings.v1p05_enable_bitmap = + FIVR_ENABLE_ALL_SX; + + config->ext_fivr_settings.vnn_enable_bitmap = + FIVR_ENABLE_ALL_SX; + + config->ext_fivr_settings.vnn_sx_enable_bitmap = + FIVR_ENABLE_ALL_SX; + + config->ext_fivr_settings.v1p05_supported_voltage_bitmap = + FIVR_VOLTAGE_NORMAL; + + config->ext_fivr_settings.vnn_supported_voltage_bitmap = + FIVR_VOLTAGE_MIN_ACTIVE; + + config->ext_fivr_settings.v1p05_voltage_mv = 1050; + config->ext_fivr_settings.vnn_voltage_mv = 780; + config->ext_fivr_settings.vnn_sx_voltage_mv = 1050; + config->ext_fivr_settings.v1p05_icc_max_ma = 500; + config->ext_fivr_settings.vnn_icc_max_ma = 500; + } +} |