diff options
| -rw-r--r-- | src/mainboard/google/brya/variants/agah/gpio.c | 31 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/agah/variant.c | 37 |
2 files changed, 55 insertions, 13 deletions
diff --git a/src/mainboard/google/brya/variants/agah/gpio.c b/src/mainboard/google/brya/variants/agah/gpio.c index 369e373808..2fc9654649 100644 --- a/src/mainboard/google/brya/variants/agah/gpio.c +++ b/src/mainboard/google/brya/variants/agah/gpio.c @@ -20,7 +20,7 @@ static const struct pad_config override_gpio_table[] = { /* A17 : DISP_MISCC ==> EN_GPU_PPVAR_GPU_NVVDD_X_PCH */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), /* A19 : DDSP_HPD1 ==> EN_PCH_PPVAR_GPU_FBVDDQ_X_L */ - PAD_CFG_GPO(GPP_A19, 0, DEEP), + PAD_CFG_GPO(GPP_A19, 1, DEEP), /* A20 : DDSP_HPD2 ==> NC */ PAD_NC(GPP_A20, NONE), /* A21 : DDPC_CTRCLK ==> EN_PP3300_GPU_X */ @@ -29,7 +29,7 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPI(GPP_A22, NONE, DEEP), /* B3 : PROC_GP2 ==> GPU_PERST_L */ - PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_GPO(GPP_B3, 0, DEEP), /* B5 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SDA */ PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), /* B6 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SCL */ @@ -75,8 +75,8 @@ static const struct pad_config override_gpio_table[] = { /* D16 : ISH_UART0_CTS# ==> NC */ PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), - /* E0 : SATAXPCIE0 ==> EN_PPVAR_GPU_NVVDD_X_ODL */ - PAD_CFG_GPO(GPP_E0, 1, DEEP), + /* E0 : SATAXPCIE0 ==> EN_PPVAR_GPU_NVVDD_X */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), /* E3 : PROC_GP0 ==> NC */ PAD_NC(GPP_E3, NONE), /* E4 : SATA_DEVSLP0 ==> PG_PPVAR_GPU_FBVDDQ_X_OD */ @@ -94,7 +94,7 @@ static const struct pad_config override_gpio_table[] = { /* E17 : RSVD_TP ==> PG_PP0950_GPU_X_OD */ PAD_CFG_GPI(GPP_E17, NONE, DEEP), /* E18 : DDP1_CTRLCLK ==> EN_PP1800_GPU_X */ - PAD_CFG_GPO(GPP_E18, 0, DEEP), + PAD_CFG_GPO_LOCK(GPP_E18, 0, LOCK_CONFIG), /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ PAD_NC(GPP_E19, NONE), /* E20 : DDP2_CTRLCLK ==> PG_PP1800_GPU_X_OD */ @@ -158,6 +158,27 @@ static const struct pad_config override_gpio_table[] = { /* S7 : SNDW3_DATA ==> SDW_HP_DATA */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1), + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/brya/variants/agah/variant.c b/src/mainboard/google/brya/variants/agah/variant.c index 979e4e02ef..b8b5af524e 100644 --- a/src/mainboard/google/brya/variants/agah/variant.c +++ b/src/mainboard/google/brya/variants/agah/variant.c @@ -4,6 +4,7 @@ #include <acpi/acpigen.h> #include <baseboard/variants.h> #include <delay.h> +#include <device/pci_ops.h> #include <gpio.h> #include <timer.h> #include <types.h> @@ -16,7 +17,7 @@ #define NVVDD_PG GPP_E16 #define PEXVDD_PWR_EN GPP_E10 #define PEXVDD_PG GPP_E17 -#define FBVDD_PWR_EN GPP_A17 +#define FBVDD_PWR_EN GPP_A19 #define FBVDD_PG GPP_E4 #define GPU_PERST_L GPP_B3 #define GPU_ALLRAILS_PG GPP_E5 @@ -45,9 +46,9 @@ struct power_rail_sequence { static const struct power_rail_sequence gpu_rails[] = { { "GPU 1.8V", GPU_1V8_PWR_EN, false, GPU_1V8_PG, }, { "NV3_3", NV33_PWR_EN, false, NV33_PG, }, - { "NVVDD+MSVDD", NVVDD_PWR_EN, true, NVVDD_PG, }, + { "NVVDD+MSVDD", NVVDD_PWR_EN, false, NVVDD_PG, }, { "PEXVDD", PEXVDD_PWR_EN, false, PEXVDD_PG, }, - { "FBVDD", FBVDD_PWR_EN, false, FBVDD_PG, }, + { "FBVDD", FBVDD_PWR_EN, true, FBVDD_PG, }, }; enum rail_state { @@ -58,10 +59,12 @@ enum rail_state { /* Assert the VR's enable pin, and wait until the VR's power-good is asserted. */ static bool sequence_rail(const struct power_rail_sequence *seq, enum rail_state state) { + enum rail_state pwr_en_state = state; + if (seq->pwr_en_active_low) - state = !state; + pwr_en_state = !pwr_en_state; - gpio_output(seq->pwr_en_gpio, state); + gpio_output(seq->pwr_en_gpio, pwr_en_state); return wait_us(DEFAULT_PG_TIMEOUT_US, gpio_get(seq->pg_gpio) == state) > 0; } @@ -105,6 +108,8 @@ static void dgpu_power_sequence_on(void) gpio_output(GPU_PERST_L, 1); printk(BIOS_INFO, "Sequenced GPU successfully\n"); + mdelay(1); + gpu_powered_on = true; } @@ -155,19 +160,35 @@ void variant_fill_ssdt(const struct device *unused) * BAR1 = bases[1] * ... */ - for (unsigned int idx = PCI_BASE_ADDRESS_0, i = 0; idx <= PCI_BASE_ADDRESS_5; - idx += sizeof(uint32_t), ++i) { + unsigned int idx, i = 0; + for (idx = PCI_BASE_ADDRESS_0; idx <= PCI_BASE_ADDRESS_5; idx += 4, ++i) { char name[ACPI_NAME_BUFFER_SIZE]; const struct resource *res; res = probe_resource(dgpu, idx); - if (!res) + if (!res || !(res->flags & IORESOURCE_STORED)) continue; snprintf(name, sizeof(name), "BAR%1d", i); acpigen_write_create_dword_field(LOCAL0_OP, idx - VGAR_BYTE_OFFSET, name); acpigen_write_store_int_to_namestr(res->base & 0xffffffff, name); + printk(BIOS_INFO, "GPU: saving %s as 0x%x\n", name, + (uint32_t)(res->base & 0xffffffff)); + + /* Also save the upper 32 bits of the BAR if applicable */ + if (!(res->flags & IORESOURCE_PCI64)) + continue; + + idx += sizeof(uint32_t); + i++; + snprintf(name, sizeof(name), "BAR%1d", i); + acpigen_write_create_dword_field(LOCAL0_OP, idx - VGAR_BYTE_OFFSET, + name); + acpigen_write_store_int_to_namestr((res->base >> 32) & 0xffffffff, + name); + printk(BIOS_INFO, "GPU: saving %s as 0x%x\n", name, + (uint32_t)((res->base >> 32) & 0xffffffff)); } /* VGAR = Local0 */ |