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-rw-r--r--src/soc/intel/alderlake/chipset.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index ed8ae049fa..e41cd842c8 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -90,6 +90,9 @@ chip soc/intel/alderlake
.tdp_pl4 = 114,
}"
+ # Reduce the size of BasicMemoryTests to speed up the boot time.
+ register "lower_basic_mem_test_size" = "true"
+
# NOTE: if any variant wants to override this value, use the same format
# as register "common_soc_config.pch_thermal_trip" = "value", instead of
# putting it under register "common_soc_config" in overridetree.cb file.