diff options
| -rw-r--r-- | src/mainboard/aopen/dxplplusu/romstage.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 6ea1261231..f203dd1f72 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> +#include <timestamp.h> #include <southbridge/intel/i82801dx/i82801dx.h> #include <northbridge/intel/e7505/raminit.h> @@ -47,6 +48,9 @@ void mainboard_romstage_entry(unsigned long bist) }, }; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + /* Get the serial port running and print a welcome banner */ lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); @@ -58,6 +62,8 @@ void mainboard_romstage_entry(unsigned long bist) if (!e7505_mch_is_ready()) { enable_smbus(); + timestamp_add_now(TS_BEFORE_INITRAM); + /* The real MCH initialisation. */ e7505_mch_init(memctrl); @@ -75,6 +81,8 @@ void mainboard_romstage_entry(unsigned long bist) /* Hook for post ECC scrub settings and debug. */ e7505_mch_done(memctrl); + + timestamp_add_now(TS_AFTER_INITRAM); } printk(BIOS_DEBUG, "SDRAM is up.\n"); |