diff options
| -rw-r--r-- | payloads/external/SeaBIOS/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/Kconfig | 13 | ||||
| -rw-r--r-- | src/arch/x86/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/mohonpeak/Kconfig | 8 |
4 files changed, 25 insertions, 0 deletions
diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 97f9d5674d..21bc9a70e8 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -31,6 +31,9 @@ ifeq ($(CONFIG_CONSOLE_SERIAL),y) else echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config endif +ifneq ($(CONFIG_SEABIOS_MALLOC_UPPERMEMORY),y) + echo "# CONFIG_MALLOC_UPPERMEMORY is not set" >> $(OUT)/seabios/.config +endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config endif diff --git a/src/Kconfig b/src/Kconfig index 97a479919e..443732a73c 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -623,6 +623,19 @@ config SEABIOS_THREAD_OPTIONROMS variations during option ROM code execution. It is not known if all option ROMs will behave properly with this option. +config SEABIOS_MALLOC_UPPERMEMORY + bool + default y + depends on PAYLOAD_SEABIOS + help + Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal + "low memory" allocations. If this is not selected, the memory is + instead allocated from the "9-segment" (0x90000-0xa0000). + This is not typically needed, but may be required on some platforms + to allow USB and SATA buffers to be written correctly by the + hardware. In general, if this is desired, the option will be + set to 'N' by the chipset Kconfig. + choice prompt "GRUB2 version" default GRUB2_MASTER diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 036dc1a7a0..aa058c01eb 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -351,6 +351,7 @@ seabios: CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ + CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) \ OUT=$(abspath $(obj)) IASL="$(IASL)" filo: diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index edf1fb8386..eb97663c7a 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -96,4 +96,12 @@ config UART_FOR_CONSOLE help The Mohon Peak board uses COM2 (2f8) for the serial console. +config SEABIOS_MALLOC_UPPERMEMORY + bool + default n + help + The Avoton/Rangeley chip does not allow devices to write into the 0xe000 + segment. This means that USB/SATA devices will not work in SeaBIOS unless + we put the SeaBIOS buffer area down in the 0x9000 segment. + endif # BOARD_INTEL_MOHONPEAK |