diff options
| -rw-r--r-- | src/soc/mediatek/mt8173/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/cbmem.c | 4 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/common_timer.c | 47 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/timer.h | 63 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/timer.c | 27 |
5 files changed, 76 insertions, 69 deletions
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index fecd7f165e..3aa463a928 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -20,6 +20,7 @@ bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c bootblock-y += i2c.c bootblock-y += pll.c bootblock-y += spi.c +bootblock-y += common_timer.c bootblock-y += timer.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) @@ -37,6 +38,7 @@ verstage-y += spi.c verstage-$(CONFIG_DRIVERS_UART) += uart.c +verstage-y += common_timer.c verstage-y += timer.c verstage-y += wdt.c verstage-$(CONFIG_SPI_FLASH) += flash_controller.c @@ -46,6 +48,7 @@ verstage-y += gpio.c romstage-$(CONFIG_SPI_FLASH) += flash_controller.c romstage-y += pll.c +romstage-y += common_timer.c romstage-y += timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c @@ -64,6 +67,7 @@ ramstage-y += cbmem.c emi.c ramstage-y += spi.c ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c ramstage-y += soc.c mtcmos.c +ramstage-y += common_timer.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += pmic_wrap.c mt6391.c i2c.c diff --git a/src/soc/mediatek/mt8173/cbmem.c b/src/soc/mediatek/mt8173/cbmem.c index 1967a2c4d3..31ea1baef4 100644 --- a/src/soc/mediatek/mt8173/cbmem.c +++ b/src/soc/mediatek/mt8173/cbmem.c @@ -19,7 +19,9 @@ #include <symbols.h> #include <soc/emi.h> +#define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB) + void *cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size(), (uintptr_t)4 * GiB); + return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/mediatek/mt8173/common_timer.c b/src/soc/mediatek/mt8173/common_timer.c new file mode 100644 index 0000000000..6e4315c7cf --- /dev/null +++ b/src/soc/mediatek/mt8173/common_timer.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <compiler.h> +#include <console/console.h> +#include <timer.h> +#include <delay.h> +#include <thread.h> + +#include <soc/addressmap.h> +#include <soc/timer.h> + +static struct mtk_gpt_regs *const mtk_gpt = (void *)GPT_BASE; + +__weak void timer_prepare(void) { /* do nothing */ } + +void timer_monotonic_get(struct mono_time *mt) +{ + mono_time_set_usecs(mt, read32(&mtk_gpt->gpt4_cnt) / GPT4_MHZ); +} + +void init_timer(void) +{ + timer_prepare(); + + /* Disable GPT4 and clear the counter */ + clrbits_le32(&mtk_gpt->gpt4_con, GPT_CON_EN); + setbits_le32(&mtk_gpt->gpt4_con, GPT_CON_CLR); + + /* Set clock source to system clock and set clock divider to 1 */ + write32(&mtk_gpt->gpt4_clk, GPT_SYS_CLK | GPT_CLK_DIV1); + /* Set operation mode to FREERUN mode and enable GTP4 */ + write32(&mtk_gpt->gpt4_con, GPT_CON_EN | GPT_MODE_FREERUN); +} diff --git a/src/soc/mediatek/mt8173/include/soc/timer.h b/src/soc/mediatek/mt8173/include/soc/timer.h index 39aacb42c2..e876971d06 100644 --- a/src/soc/mediatek/mt8173/include/soc/timer.h +++ b/src/soc/mediatek/mt8173/include/soc/timer.h @@ -13,59 +13,38 @@ * GNU General Public License for more details. */ -#ifndef __SOC_MEDIATEK_MT8173_TIMER_H__ -#define __SOC_MEDIATEK_MT8173_TIMER_H__ +#ifndef SOC_MEDIATEK_COMMON_TIMER_H +#define SOC_MEDIATEK_COMMON_TIMER_H #include <soc/addressmap.h> #include <types.h> -struct mt8173_gpt_regs { - u32 irqen; - u32 irqsta; - u32 irqack; - u32 reserved0; - u32 gpt1_con; - u32 gpt1_clk; - u32 gpt1_cnt; - u32 gpt1_compare; - u32 gpt2_con; - u32 gpt2_clk; - u32 gpt2_cnt; - u32 gpt2_compare; - u32 gpt3_con; - u32 gpt3_clk; - u32 gpt3_cnt; - u32 gpt3_compare; +#define GPT4_MHZ 13 + +struct mtk_gpt_regs { + u32 reserved[16]; u32 gpt4_con; u32 gpt4_clk; u32 gpt4_cnt; - u32 gpt4_compare; - u32 gpt5_con; - u32 gpt5_clk; - u32 gpt5_cnt; - u32 gpt5_compare; - u32 gpt6_con; - u32 gpt6_clk; - u32 gpt6_cntl; - u32 gpt6_comparel; - u32 reserved1[2]; - u32 gpt6_cnth; - u32 gpt6_compareh; - u32 apxgpt_irqmask; - u32 apxgpt_irqmask1; }; -static struct mt8173_gpt_regs *const mt8173_gpt = (void *)GPT_BASE; +check_member(mtk_gpt_regs, gpt4_con, 0x0040); +check_member(mtk_gpt_regs, gpt4_clk, 0x0044); +check_member(mtk_gpt_regs, gpt4_cnt, 0x0048); enum { - GPT_CON_EN = 0x01, - GPT_CON_CLR = 0x02, - GPT_MODE_ONE_SHOT = 0x00, - GPT_MODE_REPEAT = 0x10, - GPT_MODE_KEEP_GO = 0x20, + GPT_CON_EN = 0x01, + GPT_CON_CLR = 0x02, GPT_MODE_FREERUN = 0x30, - GPT_SYS_CLK = 0x00, - GPT_SYS_RTC = 0x01, + GPT_SYS_CLK = 0x00, + GPT_CLK_DIV1 = 0x00, }; -#endif /* __SOC_MEDIATEK_MT8173_TIMER_H__ */ +/* + * This is defined as weak no-ops that can be overridden by legacy SOCs. Some + * legacy SOCs need specific settings before init timer. And we expect future + * SOCs will not need it. + */ +void timer_prepare(void); + +#endif diff --git a/src/soc/mediatek/mt8173/timer.c b/src/soc/mediatek/mt8173/timer.c index b8d8a64c52..fd45f1d3d3 100644 --- a/src/soc/mediatek/mt8173/timer.c +++ b/src/soc/mediatek/mt8173/timer.c @@ -14,26 +14,10 @@ */ #include <arch/io.h> -#include <console/console.h> -#include <timer.h> -#include <delay.h> -#include <thread.h> - -#include <soc/addressmap.h> #include <soc/mcucfg.h> #include <soc/timer.h> -#define GPT4_MHZ 13 - -void timer_monotonic_get(struct mono_time *mt) -{ - mono_time_set_usecs(mt, read32(&mt8173_gpt->gpt4_cnt) / GPT4_MHZ); -} - -/** - * init_timer - initialize timer - */ -void init_timer(void) +void timer_prepare(void) { /* Set XGPT_IDX to 0, then the bit field of XGPT_CTL will be programmed * with following definition. @@ -48,13 +32,4 @@ void init_timer(void) write32(&mt8173_mcucfg->xgpt_idx, 0); /* Set clock mode to 13Mhz and enable XGPT */ write32(&mt8173_mcucfg->xgpt_ctl, (0x1 | ((26 / GPT4_MHZ) << 8))); - - /* Disable GPT4 and clear the counter */ - clrbits_le32(&mt8173_gpt->gpt4_con, GPT_CON_EN); - setbits_le32(&mt8173_gpt->gpt4_con, GPT_CON_CLR); - - /* Set clock source to system clock and set clock divider to 1 */ - write32(&mt8173_gpt->gpt4_clk, GPT_SYS_CLK | 0x0); - /* Set operation mode to FREERUN mode and enable GTP4 */ - write32(&mt8173_gpt->gpt4_con, GPT_CON_EN | GPT_MODE_FREERUN); } |