diff options
| -rw-r--r-- | src/cpu/intel/model_2065x/cache_as_ram.inc | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index e46a2ee3f3..21f626b9de 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -274,27 +274,6 @@ before_romstage: post_code(0x3c) -#if CONFIG_HAVE_ACPI_RESUME - movl CBMEM_BOOT_MODE, %eax - cmpl $0x2, %eax // Resume? - jne __acpi_resume_backup_done - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high - * tables memory completely, but that's a wonderful clean up task for - * another day. - */ - cld - movl $CONFIG_RAMBASE, %esi - movl CBMEM_RESUME_BACKUP, %edi - movl $HIGH_MEMORY_SAVE / 4, %ecx - rep movsl - -__acpi_resume_backup_done: -#endif - - post_code(0x3d) - __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ |