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-rw-r--r--src/cpu/amd/agesa/family14/fixme.c80
-rw-r--r--src/mainboard/amd/inagua/romstage.c1
-rw-r--r--src/mainboard/amd/persimmon/romstage.c1
-rw-r--r--src/mainboard/amd/south_station/romstage.c1
-rw-r--r--src/mainboard/amd/union_station/romstage.c1
-rw-r--r--src/mainboard/asrock/e350m1/romstage.c1
-rw-r--r--src/mainboard/gizmosphere/gizmo/romstage.c1
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/romstage.c1
-rw-r--r--src/mainboard/lippert/frontrunner-af/romstage.c1
-rw-r--r--src/mainboard/lippert/toucan-af/romstage.c1
-rw-r--r--src/northbridge/amd/agesa/agesawrapper.h1
-rw-r--r--src/northbridge/amd/agesa/family14/agesawrapper.c75
-rw-r--r--src/northbridge/amd/agesa/family15rl/agesawrapper.c4
-rw-r--r--src/northbridge/amd/agesa/family15tn/agesawrapper.c4
-rw-r--r--src/northbridge/amd/agesa/family16kb/agesawrapper.c4
15 files changed, 90 insertions, 87 deletions
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index 8d9a177215..3bcb574daf 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -97,3 +97,83 @@ void amd_initmmio(void)
PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
+
+void amd_initenv(void)
+{
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ PCI_ADDR PciAddress;
+ UINT32 PciValue;
+
+ /* Initialize Subordinate Bus Number and Secondary Bus Number
+ * In platform BIOS this address is allocated by PCI enumeration code
+ Modify D1F0x18
+ */
+ PciAddress.Address.Bus = 0;
+ PciAddress.Address.Device = 1;
+ PciAddress.Address.Function = 0;
+ PciAddress.Address.Register = 0x18;
+ /* Write to D1F0x18 */
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x00010100;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize GMM Base Address for Legacy Bridge Mode
+ * Modify B1D5F0x18
+ */
+ PciAddress.Address.Bus = 1;
+ PciAddress.Address.Device = 5;
+ PciAddress.Address.Function = 0;
+ PciAddress.Address.Register = 0x18;
+
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x96000000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize FB Base Address for Legacy Bridge Mode
+ * Modify B1D5F0x10
+ */
+ PciAddress.Address.Register = 0x10;
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x80000000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize GMM Base Address for Pcie Mode
+ * Modify B0D1F0x18
+ */
+ PciAddress.Address.Bus = 0;
+ PciAddress.Address.Device = 1;
+ PciAddress.Address.Function = 0;
+ PciAddress.Address.Register = 0x18;
+
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x96000000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize FB Base Address for Pcie Mode
+ * Modify B0D1F0x10
+ */
+ PciAddress.Address.Register = 0x10;
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x80000000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize MMIO Base and Limit Address
+ * Modify B0D1F0x20
+ */
+ PciAddress.Address.Bus = 0;
+ PciAddress.Address.Device = 1;
+ PciAddress.Address.Function = 0;
+ PciAddress.Address.Register = 0x20;
+
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x96009600;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize MMIO Prefetchable Memory Limit and Base
+ * Modify B0D1F0x24
+ */
+ PciAddress.Address.Register = 0x24;
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x8FF18001;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+}
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 6a13d03402..1a80e5ce13 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -86,6 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x41);
agesawrapper_amdinitenv();
+ amd_initenv();
post_code(0x50);
copy_and_run();
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 17da39c9d2..581c2c2858 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -93,6 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
agesawrapper_amdinitenv();
+ amd_initenv();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 53a1dce371..ccf84b61cf 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -86,6 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x41);
agesawrapper_amdinitenv();
+ amd_initenv();
post_code(0x50);
copy_and_run();
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 022b43237a..c75cf7a270 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -80,6 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x41);
agesawrapper_amdinitenv();
+ amd_initenv();
post_code(0x50);
copy_and_run();
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 911e821664..604c923fc2 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -86,6 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x41);
agesawrapper_amdinitenv();
+ amd_initenv();
post_code(0x50);
copy_and_run();
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 50cc12c502..a0c3d28b85 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -101,6 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
agesawrapper_amdinitenv();
+ amd_initenv();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index e2f43d903d..197c81d56e 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -109,6 +109,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
agesawrapper_amdinitenv();
+ amd_initenv();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index c25e1ee2c1..d21a5658cc 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -96,6 +96,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
agesawrapper_amdinitenv();
+ amd_initenv();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index c5212d7cee..e655f9a78a 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -97,6 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
agesawrapper_amdinitenv();
+ amd_initenv();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h
index 67ea637f8a..dfb8c740bc 100644
--- a/src/northbridge/amd/agesa/agesawrapper.h
+++ b/src/northbridge/amd/agesa/agesawrapper.h
@@ -48,6 +48,7 @@ void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const ch
void amd_initcpuio(void);
void amd_initmmio(void);
+void amd_initenv(void);
AGESA_STATUS agesawrapper_amdinitresume(void);
AGESA_STATUS agesawrapper_amdS3Save(void);
diff --git a/src/northbridge/amd/agesa/family14/agesawrapper.c b/src/northbridge/amd/agesa/family14/agesawrapper.c
index 5f26d85ab5..200de7e236 100644
--- a/src/northbridge/amd/agesa/family14/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family14/agesawrapper.c
@@ -125,8 +125,6 @@ AGESA_STATUS agesawrapper_amdinitenv(VOID)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
- PCI_ADDR PciAddress;
- UINT32 PciValue;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
@@ -141,80 +139,7 @@ AGESA_STATUS agesawrapper_amdinitenv(VOID)
status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
- /* Initialize Subordinate Bus Number and Secondary Bus Number
- * In platform BIOS this address is allocated by PCI enumeration code
- Modify D1F0x18
- */
- PciAddress.Address.Bus = 0;
- PciAddress.Address.Device = 1;
- PciAddress.Address.Function = 0;
- PciAddress.Address.Register = 0x18;
- /* Write to D1F0x18 */
- LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- PciValue |= 0x00010100;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
- /* Initialize GMM Base Address for Legacy Bridge Mode
- * Modify B1D5F0x18
- */
- PciAddress.Address.Bus = 1;
- PciAddress.Address.Device = 5;
- PciAddress.Address.Function = 0;
- PciAddress.Address.Register = 0x18;
-
- LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- PciValue |= 0x96000000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
- /* Initialize FB Base Address for Legacy Bridge Mode
- * Modify B1D5F0x10
- */
- PciAddress.Address.Register = 0x10;
- LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- PciValue |= 0x80000000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
- /* Initialize GMM Base Address for Pcie Mode
- * Modify B0D1F0x18
- */
- PciAddress.Address.Bus = 0;
- PciAddress.Address.Device = 1;
- PciAddress.Address.Function = 0;
- PciAddress.Address.Register = 0x18;
-
- LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- PciValue |= 0x96000000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
- /* Initialize FB Base Address for Pcie Mode
- * Modify B0D1F0x10
- */
- PciAddress.Address.Register = 0x10;
- LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- PciValue |= 0x80000000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
- /* Initialize MMIO Base and Limit Address
- * Modify B0D1F0x20
- */
- PciAddress.Address.Bus = 0;
- PciAddress.Address.Device = 1;
- PciAddress.Address.Function = 0;
- PciAddress.Address.Register = 0x20;
-
- LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- PciValue |= 0x96009600;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
- /* Initialize MMIO Prefetchable Memory Limit and Base
- * Modify B0D1F0x24
- */
- PciAddress.Address.Register = 0x24;
- LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- PciValue |= 0x8FF18001;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct);
-
return status;
}
diff --git a/src/northbridge/amd/agesa/family15rl/agesawrapper.c b/src/northbridge/amd/agesa/family15rl/agesawrapper.c
index 205b629535..c08d4f18de 100644
--- a/src/northbridge/amd/agesa/family15rl/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family15rl/agesawrapper.c
@@ -150,10 +150,6 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
status = AmdInitEnv(EnvParam);
AGESA_EVENTLOG(status, &EnvParam->StdHeader);
- /* Initialize Subordinate Bus Number and Secondary Bus Number
- * In platform BIOS this address is allocated by PCI enumeration code
- Modify D1F0x18
- */
return status;
}
diff --git a/src/northbridge/amd/agesa/family15tn/agesawrapper.c b/src/northbridge/amd/agesa/family15tn/agesawrapper.c
index 205b629535..c08d4f18de 100644
--- a/src/northbridge/amd/agesa/family15tn/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family15tn/agesawrapper.c
@@ -150,10 +150,6 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
status = AmdInitEnv(EnvParam);
AGESA_EVENTLOG(status, &EnvParam->StdHeader);
- /* Initialize Subordinate Bus Number and Secondary Bus Number
- * In platform BIOS this address is allocated by PCI enumeration code
- Modify D1F0x18
- */
return status;
}
diff --git a/src/northbridge/amd/agesa/family16kb/agesawrapper.c b/src/northbridge/amd/agesa/family16kb/agesawrapper.c
index 205b629535..c08d4f18de 100644
--- a/src/northbridge/amd/agesa/family16kb/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family16kb/agesawrapper.c
@@ -150,10 +150,6 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
status = AmdInitEnv(EnvParam);
AGESA_EVENTLOG(status, &EnvParam->StdHeader);
- /* Initialize Subordinate Bus Number and Secondary Bus Number
- * In platform BIOS this address is allocated by PCI enumeration code
- Modify D1F0x18
- */
return status;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 17:29:27 +0000