diff options
| -rw-r--r-- | src/mainboard/google/rush/romstage.c | 29 | ||||
| -rw-r--r-- | src/mainboard/google/rush_ryu/mainboard.c | 45 | ||||
| -rw-r--r-- | src/mainboard/google/rush_ryu/romstage.c | 50 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/include/soc/romstage.h | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/romstage.c | 2 |
5 files changed, 128 insertions, 0 deletions
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c index 7c01a30604..8edcba8d6a 100644 --- a/src/mainboard/google/rush/romstage.c +++ b/src/mainboard/google/rush/romstage.c @@ -51,6 +51,35 @@ void mainboard_init_tpm_i2c(void) configure_tpm_i2c_bus(); } +void mainboard_init_ec_spi(void) +{ + clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0); + + // SPI1 MOSI + pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 MISO + pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 SCLK + pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 CS0 + pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + + clock_configure_source(sbc1, CLK_M, 500); +} + +void mainboard_init_ec_i2c(void) +{ + /* Empty - Rush uses SPI to communicate with the EC */ +} + void mainboard_configure_pmc(void) { } diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c index dff5954466..140ca5f63e 100644 --- a/src/mainboard/google/rush_ryu/mainboard.c +++ b/src/mainboard/google/rush_ryu/mainboard.c @@ -20,8 +20,53 @@ #include <device/device.h> #include <boot/coreboot_tables.h> +#include <soc/clock.h> +#include <soc/nvidia/tegra132/clk_rst.h> +#include <soc/nvidia/tegra132/pinmux.h> +#include <soc/addressmap.h> + +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + +static void init_mmc(void) +{ + clock_configure_source(sdmmc4, PLLP, 48000); + + uint32_t pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE, + pin_none = PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE; + + // MMC4 (eMMC) + pinmux_set_config(PINMUX_SDMMC4_CLK_INDEX, + PINMUX_SDMMC4_CLK_FUNC_SDMMC4 | pin_none); + pinmux_set_config(PINMUX_SDMMC4_CMD_INDEX, + PINMUX_SDMMC4_CMD_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT0_INDEX, + PINMUX_SDMMC4_DAT0_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT1_INDEX, + PINMUX_SDMMC4_DAT1_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT2_INDEX, + PINMUX_SDMMC4_DAT2_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT3_INDEX, + PINMUX_SDMMC4_DAT3_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT4_INDEX, + PINMUX_SDMMC4_DAT4_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT5_INDEX, + PINMUX_SDMMC4_DAT5_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT6_INDEX, + PINMUX_SDMMC4_DAT6_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT7_INDEX, + PINMUX_SDMMC4_DAT7_FUNC_SDMMC4 | pin_up); +} + +static void setup_ec_i2c(void) +{ +} + static void mainboard_init(device_t dev) { + clock_enable_clear_reset(CLK_L_SDMMC4, 0, 0, 0, 0, 0); + + init_mmc(); + setup_ec_i2c(); } static void mainboard_enable(device_t dev) diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c index 9a41247dd8..1c08718543 100644 --- a/src/mainboard/google/rush_ryu/romstage.c +++ b/src/mainboard/google/rush_ryu/romstage.c @@ -17,10 +17,60 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/nvidia/tegra/i2c.h> +#include <soc/nvidia/tegra132/pinmux.h> +#include <soc/nvidia/tegra132/gpio.h> #include <soc/romstage.h> +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + +static void configure_tpm_i2c_bus(void) +{ + clock_configure_i2c_scl_freq(i2c3, PLLP, 19); + i2c_init(2); +} + +static void configure_ec_i2c_bus(void) +{ + clock_configure_i2c_scl_freq(i2c2, PLLP, 100); + i2c_init(1); +} + void mainboard_init_tpm_i2c(void) { + clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0); + + gpio_output(GPIO(I5), 1); + + /* I2C3 (cam) clock */ + pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, + PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + /* I2C3 (cam) data */ + pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, + PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + + configure_tpm_i2c_bus(); +} + +void mainboard_init_ec_spi(void) +{ + /* Empty - Ryu uses I2C to communicate with the EC */ +} + +void mainboard_init_ec_i2c(void) +{ + clock_enable_clear_reset(0, CLK_H_I2C2, 0, 0, 0, 0); + + /* I2C2 (GEN2) clock */ + pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX, + PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE); + /* I2C2 (GEN2) data */ + pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX, + PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE); + + configure_ec_i2c_bus(); } void mainboard_configure_pmc(void) diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h index f66912151e..dcf6ad6079 100644 --- a/src/soc/nvidia/tegra132/include/soc/romstage.h +++ b/src/soc/nvidia/tegra132/include/soc/romstage.h @@ -23,5 +23,7 @@ void mainboard_configure_pmc(void); void mainboard_enable_vdd_cpu(void); void mainboard_init_tpm_i2c(void); +void mainboard_init_ec_spi(void); +void mainboard_init_ec_i2c(void); #endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */ diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 69271f0088..be431f7975 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -68,6 +68,8 @@ void romstage(void) printk(BIOS_INFO, "T132 romstage: MTS loading done\n"); mainboard_init_tpm_i2c(); + mainboard_init_ec_spi(); + mainboard_init_ec_i2c(); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/ramstage"); |