diff options
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 13 | ||||
| -rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 28 | ||||
| -rw-r--r-- | src/soc/amd/picasso/bootblock/bootblock.c | 31 | ||||
| -rw-r--r-- | src/soc/amd/picasso/bootblock/pre_c.S | 35 |
4 files changed, 92 insertions, 15 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 3113b27783..afa18bc64c 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -14,6 +14,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select RESET_VECTOR_IN_RAM select X86_AMD_FIXED_MTRRS select X86_AMD_INIT_SIPI select ACPI_AMD_HARDWARE_SLEEP_VALUES @@ -46,10 +47,6 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select RTC -config HAVE_BOOTBLOCK - bool - default n - config AMD_FP5 def_bool y if !AMD_FT5 help @@ -219,6 +216,14 @@ config MAINBOARD_POWER_RESTORE return to S0. Otherwise the system will remain in S5 once power is restored. +config X86_RESET_VECTOR + hex + default 0x807fff0 + +config EARLYRAM_BSP_STACK_SIZE + hex + default 0x800 + menu "PSP Configuration Options" config AMDFW_OUTSIDE_CBFS diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d31e518edc..b04e1e9217 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -11,6 +11,15 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm +bootblock-y += bootblock/pre_c.S +bootblock-y += bootblock/bootblock.c +bootblock-y += southbridge.c +bootblock-y += i2c.c +bootblock-$(CONFIG_PICASSO_UART) += uart.c +bootblock-y += tsc_freq.c +bootblock-y += gpio.c +bootblock-y += smi_util.c + romstage-y += i2c.c romstage-y += romstage.c romstage-y += gpio.c @@ -29,12 +38,6 @@ verstage-y += pmutil.c verstage-$(CONFIG_PICASSO_UART) += uart.c verstage-y += tsc_freq.c -postcar-y += monotonic_timer.c -postcar-$(CONFIG_PICASSO_UART) += uart.c -postcar-y += memmap.c -postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c -postcar-y += tsc_freq.c - ramstage-y += i2c.c ramstage-y += chip.c ramstage-y += cpu.c @@ -179,8 +182,12 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DESTINATION) # type = 0x62 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img -PSP_BIOSBIN_DEST=$(CONFIG_ROMSTAGE_ADDR) -PSP_BIOSBIN_SIZE=$(CONFIG_RAM_RESET_VECTOR_STAGE_SIZE) +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +# TODO(b/154957411): Refactor amdfwtool to extract the address and size from +# the elf file. +PSP_BIOSBIN_SIZE=$(CONFIG_C_ENV_BOOTBLOCK_SIZE) +# This address must match the BOOTBLOCK logic in arch/x86/memlayout.ld. +PSP_BIOSBIN_DEST=$(shell printf "%x" $(call int-subtract, $(call int-add, $(CONFIG_X86_RESET_VECTOR) 0x10) $(PSP_BIOSBIN_SIZE))) # type = 0x63 ifeq ($(CONFIG_HAVE_ACPI_RESUME),y) @@ -368,11 +375,10 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ -USE_BIOS_FILE=$(obj)/cbfs/fallback/romstage.elf -$(PSP_BIOSBIN_FILE): $(obj)/cbfs/fallback/romstage.elf $(AMDCOMPRESS) +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(USE_BIOS_FILE) --outfile $@ --compress \ + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ --maxsize $(PSP_BIOSBIN_SIZE) ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c new file mode 100644 index 0000000000..8ae4db3178 --- /dev/null +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <bootblock_common.h> +#include <console/console.h> +#include <soc/southbridge.h> +#include <soc/i2c.h> +#include <amdblocks/amd_pci_mmconf.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + enable_pci_mmconf(); + + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + sb_reset_i2c_slaves(); + fch_pre_init(); +} + +void bootblock_soc_init(void) +{ + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + + fch_early_init(); + i2c_soc_early_init(); +} diff --git a/src/soc/amd/picasso/bootblock/pre_c.S b/src/soc/amd/picasso/bootblock/pre_c.S new file mode 100644 index 0000000000..c478ef80bb --- /dev/null +++ b/src/soc/amd/picasso/bootblock/pre_c.S @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <cpu/x86/post_code.h> + +/* + * on entry: + * mm0: BIST (ignored) + * mm2_mm1: timestamp at bootblock_protected_mode_entry + */ + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + post_code(0xa0) + + movl $_eearlyram_stack, %esp + + /* Align the stack and keep aligned for call to bootblock_c_entry() */ + and $0xfffffff0, %esp + sub $8, %esp + + movd %mm2, %eax + pushl %eax /* tsc[63:32] */ + movd %mm1, %eax + pushl %eax /* tsc[31:0] */ + + post_code(0xa2) + + call bootblock_c_entry + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever |